feat(plat/zynqmp): add support for XCK26 silicon

Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav

feat(plat/zynqmp): add support for XCK26 silicon

Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338

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Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration

plat: xilinx: zynqmp: Configure counter frequency during initialization

Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stag

plat: xilinx: zynqmp: Configure counter frequency during initialization

Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896

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plat: xilinx: common: Rename the IPI CRC checksum macro

Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.

Signed-off-by: Venkatesh Yadav Abb

plat: xilinx: common: Rename the IPI CRC checksum macro

Rename the macro ZYNQMP_IPI_CRC_CHECK to IPI_CRC_CHECK and
move the related defines to the common include.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I6d30b081ac607572a0b23e10ca8031bc90489e58

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plat:xilinx:zynqmp: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic

plat:xilinx:zynqmp: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8

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plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices

Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d,

plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices

Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe

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plat:xilinx:zynqmp: Remove the custom crash implementation

Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.

Signed-off-by: Venkatesh Yadav Abbarapu <ven

plat:xilinx:zynqmp: Remove the custom crash implementation

Removing the custom crash implementation and use
plat/common/aarch64/crash_console_helpers.S.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I045d42eb62bcaf7d1e18fbe9ab9fb9470e800215

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zynqmp: pm: Add support for PS and system reset on WDT restart

Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.

Signed-off-by: Will Wong <

zynqmp: pm: Add support for PS and system reset on WDT restart

Add ability to support PS and System reset after idling the APU,
by reading the restart scope from the PMU.

Signed-off-by: Will Wong <willw@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I23c01725d8ebb71ad34be02ab204411b93620702

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zynqmp: pm: Update PM version and support PM version check

ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.

Signed-off-by:

zynqmp: pm: Update PM version and support PM version check

ATF is not checking PM version. Add version check in such
a way that it is compatible with current and newer version
of PM.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ia095d118121e6f75e8d320e87d5e2018068fa079

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plat: xilinx: Fix non-MISRA compliant code

This patch fixes the non compliant code like missing braces for
conditional single statement bodies.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.ab

plat: xilinx: Fix non-MISRA compliant code

This patch fixes the non compliant code like missing braces for
conditional single statement bodies.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I95b410ae5950f85dc913c4448fcd0a97e0fd490c

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Merge changes from topic "xilinx-sd-tap-delay" into integration

* changes:
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
plat: zynqmp: Check for DLL status before doing reset

xilinx: zynqmp: Add support for Error Management

Adding the EM specific smc handler for the EM-related requests.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-b

xilinx: zynqmp: Add support for Error Management

Adding the EM specific smc handler for the EM-related requests.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98122d49604a01a2f6bd1e509a5896ee68069dd0

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zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse

This patch adds new api to access zynqmp efuse memory

Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.

zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse

This patch adds new api to access zynqmp efuse memory

Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I0971ab6549552a6f96412431388d19b822db00ab

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zynqmp : pm : Adds new zynqmp-pm api SMC call for register access

This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.

Signed-off-by: Kalyani Akula <kalyan

zynqmp : pm : Adds new zynqmp-pm api SMC call for register access

This patch adds new zynqmp-pm api to provide read/write access to
CSU or PMU global registers.

Signed-off-by: Kalyani Akula <kalyania@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I4fd52eb732fc3e6a8bccd96cad7dc090b2161042

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zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls

Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros a

zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls

Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I51f2285a79f202cb2ca9f031044002e16dd1e92f

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zynqmp: pm: Reimplement pinctrl set/get function EEMI API

Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
t

zynqmp: pm: Reimplement pinctrl set/get function EEMI API

Functions are reimplemented to issue system-level pinctrl EEMI calls
to the PMU-FW rather than using MMIO read/write. Macros and functions
that appear to be unused after the change is made are removed.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I21b8fda855aa69090b85d6aaf411e19560201cb5

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zynqmp: pm: Implement pinctrl request/release EEMI API

The calls are just passed through to the PMU-FW. Before issuing
other pinctrl functions the pin should be successfully requested.

Signed-off-b

zynqmp: pm: Implement pinctrl request/release EEMI API

The calls are just passed through to the PMU-FW. Before issuing
other pinctrl functions the pin should be successfully requested.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibce280edebedf779b3962009c274d0b3d928e0e4

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zynqmp: pm: Update return type in query functions

In pm_query_data() function return type is stored in response so
there is no use of return type. Update return type of function
pm_query_data() from

zynqmp: pm: Update return type in query functions

In pm_query_data() function return type is stored in response so
there is no use of return type. Update return type of function
pm_query_data() from enum pm_ret_status to void. Similarly
update return type of pm_api_clock_get_name() and
pm_api_pinctrl_get_function_name() functions.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Id811926f0b4ebcc472480bb94f3b88109eb036cd

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plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay

This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before aut

plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay

This patch disable the ITAPDLYENA bit for ITAP delay value zero.
As per IP design, it is recommended to disable the ITAPDLYENA bit
before auto-tuning.
Also disable OTAPDLYENA bit always as there is one issue in RTL
where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1
controllers. Hence it is recommended to disable OTAPDLYENA bit always
for both the controllers.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Srinivas Goud <srinivas.goud@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Icf035cb63510ac7bec4e9d523a622f145eaf0989

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plat: zynqmp: Check for DLL status before doing reset

This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL rese

plat: zynqmp: Check for DLL status before doing reset

This patch check for the DLL status before doing the DLL reset.
If DLL reset is already issued then skip the reset inside ATF
otherwise DLL reset will be issued.
By doing this way, all the following cases will be supported.
1. Patched ATF + Patched Linux base.
2. Older ATF + Patched Linux base.
3. Patched ATF + Older Linux base.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I53a0a27521330f1543275cc9cb44cd1dfc569c65

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zynqmp: pm: Update flags in common clk divisor node

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does

zynqmp: pm: Update flags in common clk divisor node

Current implementation doesn't support change of div1 value if clk
has 2 divisor because div1 clk is the parent of the div2 clk and div2
clk does not have SET_RATE_PARENT flag.
This causes div1 value to be fixed and only value of div2 will be
adjusted according to required clock rate.

Example:
Consider a case of nand_ref clock which has 2 divisor and 1 mux.
The frequency of mux clock is 1500MHz and default value of div1 and
div2 is 15 and 1 respectively. So the final clock will be of 100MHz.
When driver requests 80MHz for nand_ref clock, clock framework will
adjust the div2 value to 1 (setting div2 value 2 results final clock
to 50MHz which is more inaccurate compare to 100Mhz) which results
final clock to 100MHz.
Ideally the value of div1 and div2 should be updated to 19 and 1
respectively so that final clock goes to around 78MHz.

This patch fixes above problem by allowing change in div1 value.

Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58

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zynqmp: pm_api_clock: Copy only the valid bytes

This patches copies only the valid part of string and
avoids filling junk at the end.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@

zynqmp: pm_api_clock: Copy only the valid bytes

This patches copies only the valid part of string and
avoids filling junk at the end.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: If23772f31f9cf7f5042e8bfc474fbfe77dcd90e7

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plat: xilinx: zynqmp: Enable log messages for debug

Save some space by enabling the log messages like bl33 address
only for debug builds. Also check the bl33 and bl32 address and
print only if this

plat: xilinx: zynqmp: Enable log messages for debug

Save some space by enabling the log messages like bl33 address
only for debug builds. Also check the bl33 and bl32 address and
print only if this is not NULL.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I58d846bf69a75e839eb49abcbb9920af13296886

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plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG

For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. S

plat: zynqmp: Change macro name of PM_BOOT_HEALTH_STATUS_REG

For boot health status PMU Global General Storage Register 4 is
used. GGS4 can be used for other purpose along with boot health
status. So, change its name from PM_BOOT_HEALTH_STATUS_REG
to PMU_GLOBAL_GEN_STORAGE4.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I2f5c4c6a161121e7cdb4b9f0f8711d0dad16c372

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plat: xilinx: zynqmp: Include GICv2 makefile

Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done

plat: xilinx: zynqmp: Include GICv2 makefile

Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done in the commit #1322dc94f7.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8

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