| e682d38b | 02-Feb-2022 |
Michal Simek <michal.simek@xilinx.com> |
feat(zynqmp): pm_api_clock_get_num_clocks cleanup
There is no reason to have even one additional useless line that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-
feat(zynqmp): pm_api_clock_get_num_clocks cleanup
There is no reason to have even one additional useless line that's why remove it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: Icc3c74249dfe64173aa5c88fb0f9ffe7576fc2aa
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| 223a6284 | 21-Dec-2021 |
Ronak Jain <ronak.jain@xilinx.com> |
feat(zynqmp): add feature check support
This API returns version of supported APIs.
Here, there are three cases to check API version by using feature check implementation.
1. Completely implemente
feat(zynqmp): add feature check support
This API returns version of supported APIs.
Here, there are three cases to check API version by using feature check implementation.
1. Completely implemented in TF-A: I mean the EEMI APIs which are completely implemented in the TF-A only. So check those IDs and return appropriate version for the same. Right now, it is base version.
2. Completely implemented in firmware: I mean the EEMI APIs which are completely implemented in the firmware only. Here, TF-A only passes Linux request to the firmware to get the version of supported API. So check those IDs and send request to firmware to get the version and return to Linux if the version is supported or return the error code if the feature is not supported.
3. Partially implemented (Implemented in TF-A and firmware both): First check dependent EEMI API version with the expected version in the TF-A. If the dependent EEMI API is supported in firmware then return its version and check with the expected version in the TF-A. If the version matches then check for the actual requested EEMI API version. If the version is supported then return version of API implemented in TF-A.
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: I73f20d8222c518df1cda7879548b408b130b5b2e
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| a469c1e1 | 21-Jan-2022 |
Ronak Jain <ronak.jain@xilinx.com> |
fix(zynqmp): use common interface for eemi apis
Currently all EEMI API has its own implementation in TF-A which is redundant. Most EEMI API implementation in TF-A does same work. It prepares payload
fix(zynqmp): use common interface for eemi apis
Currently all EEMI API has its own implementation in TF-A which is redundant. Most EEMI API implementation in TF-A does same work. It prepares payload received from kernel, sends payload to firmware, receives response from firmware and send response back to kernel.
So use common interface for EEMI APIs which has similar functionality. This will optimize TF-A code.
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: I07325644a1fae80211f2588d5807c21973f6d48f
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| cc077c22 | 13-Jan-2022 |
Nava kishore Manne <nava.manne@xilinx.com> |
feat(zynqmp): add support to get info of xilfpga
Adds support to get the xilfpga library version and feature list info.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Rona
feat(zynqmp): add support to get info of xilfpga
Adds support to get the xilfpga library version and feature list info.
Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: Iff10ad2628a6a90230c18dc3aebf9dde89f53ecd
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| 578f468a | 11-Aug-2021 |
Ronak Jain <ronak.jain@xilinx.com> |
feat(plat/xilinx/zynqmp): add support for runtime feature config
Add support for runtime feature configuration which are running on the firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and
feat(plat/xilinx/zynqmp): add support for runtime feature config
Add support for runtime feature configuration which are running on the firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and IOCTL_GET_FEATURE_CONFIG for configuring the features.
Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: I976aef15932783a25396b2adeb4c8f140cc87e79
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| 1f910194 | 23-Nov-2020 |
VNSL Durga <vnsl.durga.challa@xilinx.com> |
zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
This patch adds new api to access zynqmp efuse memory
Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com> Signed-off-by: Rajan Vaja <rajan.
zynqmp:pm: Adds new zynqmp-pm api SMC call for efuse
This patch adds new api to access zynqmp efuse memory
Signed-off-by: VNSL Durga <vnsl.durga.challa@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I0971ab6549552a6f96412431388d19b822db00ab
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| 95c3ebcb | 23-Nov-2020 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
Functions are reimplemented to issue system-level pinctrl EEMI calls to the PMU-FW rather than using MMIO read/write. Macros a
zynqmp: pm: Reimplement pinctrl get/set config parameter EEMI API calls
Functions are reimplemented to issue system-level pinctrl EEMI calls to the PMU-FW rather than using MMIO read/write. Macros and functions that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I51f2285a79f202cb2ca9f031044002e16dd1e92f
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| 10a346d9 | 13-Sep-2018 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
Functions are reimplemented to issue system-level pinctrl EEMI calls to the PMU-FW rather than using MMIO read/write. Macros and functions t
zynqmp: pm: Reimplement pinctrl set/get function EEMI API
Functions are reimplemented to issue system-level pinctrl EEMI calls to the PMU-FW rather than using MMIO read/write. Macros and functions that appear to be unused after the change is made are removed.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I21b8fda855aa69090b85d6aaf411e19560201cb5
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| 43a029cb | 13-Sep-2018 |
Mirela Simonovic <mirela.simonovic@aggios.com> |
zynqmp: pm: Implement pinctrl request/release EEMI API
The calls are just passed through to the PMU-FW. Before issuing other pinctrl functions the pin should be successfully requested.
Signed-off-b
zynqmp: pm: Implement pinctrl request/release EEMI API
The calls are just passed through to the PMU-FW. Before issuing other pinctrl functions the pin should be successfully requested.
Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Ibce280edebedf779b3962009c274d0b3d928e0e4
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| fe1fa205 | 30-Oct-2020 |
Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> |
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
This patch disable the ITAPDLYENA bit for ITAP delay value zero. As per IP design, it is recommended to disable the ITAPDLYENA bit before aut
plat: zynqmp: Disable ITAPDLYENA bit for zero ITAP delay
This patch disable the ITAPDLYENA bit for ITAP delay value zero. As per IP design, it is recommended to disable the ITAPDLYENA bit before auto-tuning. Also disable OTAPDLYENA bit always as there is one issue in RTL where SD0_OTAPDLYENA has been wrongly connected to both SD0 and SD1 controllers. Hence it is recommended to disable OTAPDLYENA bit always for both the controllers.
Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Acked-by: Srinivas Goud <srinivas.goud@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Icf035cb63510ac7bec4e9d523a622f145eaf0989
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| c8f62536 | 18-Sep-2018 |
Ravi Patel <ravi.patel@xilinx.com> |
zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk has 2 divisor because div1 clk is the parent of the div2 clk and div2 clk does
zynqmp: pm: Update flags in common clk divisor node
Current implementation doesn't support change of div1 value if clk has 2 divisor because div1 clk is the parent of the div2 clk and div2 clk does not have SET_RATE_PARENT flag. This causes div1 value to be fixed and only value of div2 will be adjusted according to required clock rate.
Example: Consider a case of nand_ref clock which has 2 divisor and 1 mux. The frequency of mux clock is 1500MHz and default value of div1 and div2 is 15 and 1 respectively. So the final clock will be of 100MHz. When driver requests 80MHz for nand_ref clock, clock framework will adjust the div2 value to 1 (setting div2 value 2 results final clock to 50MHz which is more inaccurate compare to 100Mhz) which results final clock to 100MHz. Ideally the value of div1 and div2 should be updated to 19 and 1 respectively so that final clock goes to around 78MHz.
This patch fixes above problem by allowing change in div1 value.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: Ibb98f6748d28653fdd1e59bf433b6a37ce9c1a58
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| a8b10c64 | 24-Aug-2018 |
Davorin Mista <davorin.mista@aggios.com> |
zynqmp: pm: update error codes to match Linux and PMU Firmware
All EEMI error codes start with value 2000.
Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by current ATF code have
zynqmp: pm: update error codes to match Linux and PMU Firmware
All EEMI error codes start with value 2000.
Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by current ATF code have been left in place.
Signed-off-by: Davorin Mista <davorin.mista@aggios.com> Acked-by: Will Wong <WILLW@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6
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