fix(zynqmp): resolve runtime error in TSP

TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case

fix(zynqmp): resolve runtime error in TSP

TSP(bl32) requires secure interrupts to be handled at S-EL1.
Enable the ZynqMP to handle secure interrupts in S-EL1 by setting
GICV2_G0_FOR_EL3 to 0 in case of SPD=tspd build option.

For ZYNQMP_WDT_RESTART build option GICV2_G0_FOR_EL3 needs to be
enabled and thus for ZynqMP GICV2_G0_FOR_EL3 is set to 1 by default.
On GICv2, when GICV2_G0_FOR_EL3 is set to 1, Group 0 interrupts
target EL3. This allows GICv2 platforms to enable features requiring
EL3 interrupt type.

This also means that all GICv2 Group 0 interrupts are delivered
to EL3, and the Secure Payload interrupts needs to be synchronously
handed over to Secure EL1 for handling.

Change-Id: I7eb72c6588ab41730a74ece261050840646de037
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "xlnx_zynqmp_changes" into integration

* changes:
feat(zynqmp): build pm code as library
chore(zynqmp): print entry address to Secure and NS world

feat(zynqmp): build pm code as library

Build Platform Management(PM) code as an Library.
Building PM code as library provides an option to switch to different
firmware interfaces like custom package

feat(zynqmp): build pm code as library

Build Platform Management(PM) code as an Library.
Building PM code as library provides an option to switch to different
firmware interfaces like custom packages.

Change-Id: I872d45edf55ac83a6efb86591d12a0fef7b598cb
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "fix(zynqmp): conditional reservation of memory in DTB" into integration

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This create

fix(zynqmp): conditional reservation of memory in DTB

When the TF-A is placed in DDR memory range, the DDR memory range is
getting explicitly reserved in the default device tree by TF-A.
This creates an error condition in the use case where Device tree is
not present or it is present at a different location.

To fix this, a new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is
introduced. The TF-A will reserve the DDR memory only when a valid
DTB address is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired
DDR address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I846fa373ba9f7c984eda3a55ccaaa622082cad81
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "feat(zynqmp): add support for custom sip service" into integration

feat(zynqmp): add support for custom sip service

Add support for custom sip service.
Bare minimum implementation for custom_smc_handler is provided
by platform. Actual definition for custom_smc_hand

feat(zynqmp): add support for custom sip service

Add support for custom sip service.
Bare minimum implementation for custom_smc_handler is provided
by platform. Actual definition for custom_smc_handler will be provided
by custom pkg.

This feature is going to be used by external libraries. For example
for checking it's status.

The similar approach is also used by qti/{sc7180,sc7280} platforms
by providing a way to select QTISECLIB_PATH.

This code is providing a generic way how to wire any code
via custom $(CUSTOM_PKG_PATH)/custom_pkg.mk makefile with also an
option to wire custom SMC. SMC functionality depends on "package".

Change-Id: Icedffd582f76f89fc399b0bb2e05cdaee9b743a0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>

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Merge "fix(zynqmp): enable A53 workaround(errata 1530924)" into integration

fix(zynqmp): enable A53 workaround(errata 1530924)

BL31 already reports that there is missing CPU workaround for this
erratum as
"WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!"

fix(zynqmp): enable A53 workaround(errata 1530924)

BL31 already reports that there is missing CPU workaround for this
erratum as
"WARNING: BL31: cortex_a53: CPU workaround for 1530924 was missing!"

That's why enable it by default as was done by other platforms for
example by commit 74665119f04d ("allwinner: Enable workaround for
Cortex-A53 erratum 1530924").

Change-Id: I251ffe3c307781b07477afb64f4e7af5dd9af9fe
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL

Merge changes from topic "provencore-spd" into integration

* changes:
feat(zynqmp): add support for ProvenCore
feat(services): add a SPD for ProvenCore
feat(gic): add APIs to raise NS and S-EL1 SGIs

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feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is

feat(zynqmp): add support for ProvenCore

ProvenCore requires secure SGIs to be handled at S-EL1. This patch
overrides the default ZynqMP configuration to handle them at EL3 in case
ProvenCore SPD is enabled.

Signed-off-by: Jeremie Corbier <jeremie.corbier@provenrun.com>
Signed-off-by: Mélanie Favre <melanie.favre@provenrun.com>
Change-Id: I2e36d2983f82fbb9b7acf7e18791b8ed92811b60

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Merge "feat(zynqmp): protect eFuses from non-secure access" into integration

feat(zynqmp): protect eFuses from non-secure access

When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.

This enables eFu

feat(zynqmp): protect eFuses from non-secure access

When configuration option ZYNQMP_SECURE_EFUSES is defined then Xilinx
ZynqMP's PS eFuses can only be accesses from secure state.

This enables eFuses to be reserved and protected only for security use
cases for example in OP-TEE.

Change-Id: I866905e35ce488f50f5f6e1b4667b08a9fa2386d
Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>

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Merge "fix(xilinx): miscellaneous fixes for xilinx platforms" into integration

fix(xilinx): miscellaneous fixes for xilinx platforms

This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal S

fix(xilinx): miscellaneous fixes for xilinx platforms

This patch gathers miscellaneous minor fixes to the xilinx
platforms like tabs for indentation and misra 10.1 warnings.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4cdb89ffec7d5abc64e065ed5b5e5d10b30ab9f9

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Merge "fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1" into integration

fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1

Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using
v1 library of translation tables.

With upstream patch d323af9e3d903d981b42f954844a95a6bfef91ab

fix(zynqmp): define and enable ARM_XLAT_TABLES_LIB_V1

Enable ARM_XLAT_TABLES_LIB_V1 as ZynqMP is using
v1 library of translation tables.

With upstream patch d323af9e3d903d981b42f954844a95a6bfef91ab,
the usage of MAP_REGION_FLAT is referring to definition in file
include/lib/xlat_tables/xlat_tables_v2.h but while preparing
xlat tables in lib/xlat_tables/xlat_tables_common.c it is referring
to include/lib/xlat_tables/xlat_tables.h which is v1 xlat tables.
Also, ZynqMP was using v1 so defined ARM_XLAT_TABLES_LIB_V1 to
use v1 xlat tables everywhere.
This fixes the issue of xlat tables failures as it takes v2
library mmap_region structure in some files and v1 in other
files.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ibc0e1c536e19f4edd6a6315bf1b0dfcec33e2fdc

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Merge "fix(xilinx): fix coding style violations" into integration

fix(xilinx): fix coding style violations

Fix coding style violations and alignments:
- Remove additional newlines in headers
- Remove additional newlines in code
- Add newline to separate variable f

fix(xilinx): fix coding style violations

Fix coding style violations and alignments:
- Remove additional newlines in headers
- Remove additional newlines in code
- Add newline to separate variable from the code
- Use the same indentation in platform.mk
- Align function parameters
- Use tabs for indentation in kernel-doc format

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I0b12804ff63bc19778e8f21041f9accba5b488b9

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Merge "feat(plat/zynqmp): disable the -mbranch-protection flag" into integration

feat(plat/zynqmp): disable the -mbranch-protection flag

With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP u

feat(plat/zynqmp): disable the -mbranch-protection flag

With new gcc11.2 by default the -mbranch-protection is
set to "standard" which is leading to increase the text
section by 4Kb. As the ZynqMP uses the ARMv8 architecture,
so there is no impact when we disable the branch protection.
These instructions do not provide the branch protection in
architectures before Armv8.3-A.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I36f7a55abf99f50df2ee265255598d83b1f480c6

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Merge "feat(plat/zynqmp): extend DT description by TF-A" into integration

feat(plat/zynqmp): extend DT description by TF-A

In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can b

feat(plat/zynqmp): extend DT description by TF-A

In case of TF-A running out of DDR there is a need to reserved
memory to let other SW know that none can't use this memory. HW
wise this region can be (and should be) also protected by
protection unit XMPU. This is the first step to add reserved
memory location to DT.

DT address corresponds with default address in U-Boot and also
default address in Xilinx BSPs.

Code is valid only when TF-A runs out of DDR. When it runs out
of OCM there is no need to reseve anything because OCM is hidden
to OS.

Change-Id: I01f230ced67207a159128cc11d11d36dd4590cab
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

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