Merge "refactor(plat/zynqmp): optimize the code to save some space" into integration

refactor(plat/zynqmp): optimize the code to save some space

As there is constraint with the space for the release builds,
remove some of the legacy code.

Signed-off-by: Venkatesh Yadav Abbarapu <ve

refactor(plat/zynqmp): optimize the code to save some space

As there is constraint with the space for the release builds,
remove some of the legacy code.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I5b8b16f34ed8e480f16ab1aeac80b85cdb391852

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Merge "feat(plat/zynqmp): add support for XCK26 silicon" into integration

feat(plat/zynqmp): add support for XCK26 silicon

Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav

feat(plat/zynqmp): add support for XCK26 silicon

Add support for XCK26 silicon which is available on SOM board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Ic98213328702903af8a79f487a2868f3e6d60338

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Merge "plat: xilinx: zynqmp: Configure counter frequency during initialization" into integration

plat: xilinx: zynqmp: Configure counter frequency during initialization

Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stag

plat: xilinx: zynqmp: Configure counter frequency during initialization

Counter frequency for generic timer of Arm-A53 based Application
Processing Unit(APU) is not configuring in case if First Stage Boot
Loader(FSBL) does not initialize counter frequency. This happens
when FSBL is running from Arm-R5 based Real-time Processing Unit(RPU).
Because of that generic timer driver functionality is not working.
So configure counter frequency during initialization.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: Icfccd59d7d2340fba25ebfb2ef6a813af4290896

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Merge "plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices" into integration

plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices

Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d,

plat: xilinx: zynqmp: Add missing ids for 43/46/47dr devices

Add support for ZU43DR, ZU46DR and ZU47DR to the list of zynqmp
devices. The ZU43DR, ZU46DR and ZU47DR RFSoC silicon id values are
0x7d, 0x78 and 0x7f.

Signed-off-by: Sandeep Gundlupet Raju <sandeep.gundlupet-raju@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I566f707116d83475de7c87a6004ca96bf7bccebe

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Merge changes from topic "add-versal-soc-support" into integration

* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks

Merge changes from topic "add-versal-soc-support" into integration

* changes:
zynqmp: pm: Add LPD WDT clock to the pm_clock structure
zynqmp: pm: Fix clock models and IDs of GEM-related clocks
zynqmp: pm: Rename FPD WDT clock ID
plat: xilinx: zynqmp: Correct syscnt freq for QEMU
arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR
arm64: zynqmp: Add id for new RFSoC device ZU39DR

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plat: xilinx: zynqmp: Correct syscnt freq for QEMU

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jol

plat: xilinx: zynqmp: Correct syscnt freq for QEMU

Correct the syscnt frequency for ZynqMP QEMU to 65Mhz.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ie0137feb9b7e24ed4e5d6cbf81c58ac77bb69214

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arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values o

arm64: zynqmp: Add idcodes for new RFSoC silicons ZU48DR and ZU49DR

Add support for zu48dr and zu49dr to the list of zynqmp devices. The
zu48dr and zu49dr are the new RFSoC silicons with id values of 0x7b
and 0x7e.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I2978f16bb663853951ef8059bf0327f909447f34

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arm64: zynqmp: Add id for new RFSoC device ZU39DR

This patch adds new RFSoC device ZU39DR to zynqmp
devices list

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-of

arm64: zynqmp: Add id for new RFSoC device ZU39DR

This patch adds new RFSoC device ZU39DR to zynqmp
devices list

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I35735da9e7d7facbde44323c49eac1b714e4909d

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Merge "plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()" into integration

plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()

Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initializ

plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()

Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initialization from sip_svc_setup() to zynqmp_config_setup().

Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>

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Merge pull request #1744 from jollysxilinx/integration

plat: xilinx: code restructure

plat: xilinx: zynqmp: Move zynqmp_private.h to include directory

Move zynqmp_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So,

plat: xilinx: zynqmp: Move zynqmp_private.h to include directory

Move zynqmp_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>

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Merge pull request #1726 from antonio-nino-diaz-arm/an/includes

Sanitise includes across codebase

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- inclu

Sanitise includes across codebase

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

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Merge pull request #1557 from sivadur/integration

Xilinx latest platform related changes

zynqmp: Remove emulation platform support

This patch removes support for emulation platforms
EP108 and Veloce.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

Merge pull request #1433 from sivadur/integration

xilinx: fix zynqmp build when tsp is enabled

plat: xilinx: zynqmp: Get chipid from registers for BL32

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should

plat: xilinx: zynqmp: Get chipid from registers for BL32

This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should always be accessed from APU in their system configuration.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>

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Merge pull request #1369 from sivadur/xilinxdiff

Xilinx platform mangement related changes

zynqmp: Fix EG/EV detection logic

The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, dis

zynqmp: Fix EG/EV detection logic

The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, display
EG/EV as a part of string. The PL powerup status will
be filled by pmufw based on PL PROGB status in the
9th bit of version field.This patch also used IPI
to get this info from pmufw instead of directly accessing
the registers. Accessing this info from pmufw using
IPI fixes the issue of PMUFW access denied error for
reading IPDISABLE register.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>

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xilinx: zynqmp: Remove PMU Firmware checks

Xilinx now requires the PMU FW when using ATF, so it doesn't make sense
to maintain checks for the PMU FW in ATF. This also means that cases
where ATF came

xilinx: zynqmp: Remove PMU Firmware checks

Xilinx now requires the PMU FW when using ATF, so it doesn't make sense
to maintain checks for the PMU FW in ATF. This also means that cases
where ATF came up before the PMU FW (such as on QEMU) ATF will now hang
waiting for the PMU FW instead of aborting.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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