| #
e7644eb6 |
| 04-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "chore(xilinx): reorder include files as per TF-A guidelines" into integration
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| #
01a326ab |
| 22-Jun-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
chore(xilinx): reorder include files as per TF-A guidelines
This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rear
chore(xilinx): reorder include files as per TF-A guidelines
This commit reorders the include files in accordance with the
guidelines provided by Trusted Firmware-A (TF-A).
The include files are rearranged to ensure a consistent and
organized structure in the codebase, facilitating better
readability and maintainability.
https: //trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html#headers-and-inclusion
https://git.trustedfirmware.org/ci/tf-a-ci-scripts.git/tree/script/static-checks/
For example, to run header check:
/tf-a-ci-scripts/script/static-checks/check-include-order.py --tree ${PWD} > Includefileorder.txt
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: Ia5802722e69859596b94f31ec40755adbf7d865b
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| #
76778ffa |
| 24-May-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(zynqmp): make zynqmp_devices structure smaller" into integration
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| #
7e3e7999 |
| 27-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
fix(zynqmp): make zynqmp_devices structure smaller
Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.
Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516
fix(zynqmp): make zynqmp_devices structure smaller
Pack the structure and make id/ver smaller and sorted.
The change saves 400bytes in RODATA section.
Change-Id: I8bcbe8fd589ba193551a0dd2cd19572516252e73
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
d84171b4 |
| 20-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
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| #
619bc13e |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
523389e7 |
| 28-Mar-2023 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(xilinx): move versal files to common place" into integration
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| #
a92681d9 |
| 22-Dec-2022 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
refactor(xilinx): move versal files to common place
Moved necessary files to common place so that it can be used for
Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id
refactor(xilinx): move versal files to common place
Moved necessary files to common place so that it can be used for
Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I611fa849207b082e6599acfb65c55d27b9c99435
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| #
fb9d95e3 |
| 14-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): add SMCCC_ARCH_SOC_ID support" into integration
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| #
8f9ba3f3 |
| 09-Feb-2023 |
Michal Simek <michal.simek@amd.com> |
feat(zynqmp): add SMCCC_ARCH_SOC_ID support
Add support for calling SMCCC_ARCH_SOC_ID which is used by Linux soc_id
driver for printing information about manufacturer and also chip version
and silic
feat(zynqmp): add SMCCC_ARCH_SOC_ID support
Add support for calling SMCCC_ARCH_SOC_ID which is used by Linux soc_id
driver for printing information about manufacturer and also chip version
and silicon ID code. SOC revision is directly mapped to chip ID code.
And SOC version is composed from manufacturer ID based on JEP-106 with
chip_id which contains bits mapped to CPU register 0xffca0044 platform
bits which differentiate between silicon, qemu and other emulated
platforms.
Function description is available at
docs/getting_started/porting-guide.rst.
Change-Id: I1f19e1973593897e71b39244dbdbceb6bd0e8a07
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
1548e0e7 |
| 02-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_feat_chores" into integration
* changes:
chore(xilinx): update print information
feat(versal-net): add jtag dcc support
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| #
d6760c4d |
| 18-Jan-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
chore(xilinx): update print information
Remove company name from the console messages while printing only
relevant information for the platform.
Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd
chore(xilinx): update print information
Remove company name from the console messages while printing only
relevant information for the platform.
Change-Id: Id8171326e0267eb6f3a26de4eb66143970de2dbd
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| #
95cde795 |
| 18-Jan-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(zynqmp): fix xck24 silicon ID" into integration
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| #
f1565907 |
| 18-Jan-2023 |
Michal Simek <michal.simek@amd.com> |
fix(zynqmp): fix xck24 silicon ID
Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99
fix(zynqmp): fix xck24 silicon ID
Origin ID code has changed from origin description. After receiving part
new ID code come up that's why fix it. The origin ID code has been added
by commit 86869f99d0c1 ("feat(zynqmp): add support for xck24 silicon").
Change-Id: I727bfe43fd7ef9e604f63bde5fa37fa3666db8c4
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
89666eb3 |
| 07-Jul-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): resolve the misra 10.1 warnings" into integration
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| #
bfd7c881 |
| 04-Jul-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The op
feat(zynqmp): resolve the misra 10.1 warnings
MISRA Violation: MISRA-C:2012 R.10.1
1) The expression of non-boolean essential type is being interpreted as a
boolean value for the operator.
2) The operand to the operator does not have an essentially unsigned type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I97bbc056f4fee167742429e144144ba793bf77b3
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| #
57ab7497 |
| 29-Jun-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_zynqmp_misra_fix1" into integration
* changes:
fix(zynqmp): resolve the misra 8.6 warnings
fix(zynqmp): resolve the misra 4.6 warnings
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| #
bc779e16 |
| 13-Jun-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(zynqmp): add support for xck24 silicon" into integration
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| #
86869f99 |
| 17-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
feat(zynqmp): add support for xck24 silicon
Add support for new xck24 device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilin
feat(zynqmp): add support for xck24 silicon
Add support for new xck24 device.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I913a34d5a48ea665aaa4348f573fc59566dd5a9b
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| #
ffa91031 |
| 19-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(zynqmp): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by:
fix(zynqmp): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I9fb686e7aa2b85af6dfcb7bb5f87eddf469fb85c
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| #
fad4a717 |
| 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "xlnx_zynqmp_misra" into integration
* changes:
fix(zynqmp): resolve misra R14.4 warnings
fix(zynqmp): resolve misra R16.3 warnings
fix(zynqmp): resolve misra R15.7 wa
Merge changes from topic "xlnx_zynqmp_misra" into integration
* changes:
fix(zynqmp): resolve misra R14.4 warnings
fix(zynqmp): resolve misra R16.3 warnings
fix(zynqmp): resolve misra R15.7 warnings
fix(zynqmp): resolve misra R15.6 warnings
fix(zynqmp): resolve misra 7.2 warnings
fix(zynqmp): resolve misra R10.3
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| #
dd1fe717 |
| 04-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(zynqmp): resolve misra R14.4 warnings
MISRA Violation: MISRA-C:2012 R.14.4
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essen
fix(zynqmp): resolve misra R14.4 warnings
MISRA Violation: MISRA-C:2012 R.14.4
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean type.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I8f3f6f956d1d58ca201fb5895f12bcaabf2afd3b
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| #
eb0d2b17 |
| 29-Apr-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(zynqmp): resolve misra R15.6 warnings
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.
Signed-off-by: Venkates
fix(zynqmp): resolve misra R15.6 warnings
MISRA Violation: MISRA-C:2012 R.15.6
- The body of an iteration-statement or a selection-statement shall be
a compound statement.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0fc8eeac0e592f00297a1ac42a1ba3df1144733b
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| #
a0cad7ce |
| 29-Apr-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(zynqmp): update the log message to verbose" into integration
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| #
1277af9b |
| 12-Apr-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(zynqmp): update the log message to verbose
Changing the log message from notice to verbose, to save some space
and that leads to successfull compilation.
Signed-off-by: Venkatesh Yadav Abbarapu
fix(zynqmp): update the log message to verbose
Changing the log message from notice to verbose, to save some space
and that leads to successfull compilation.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: Iee5a808febf211464eb8ba6f0377f79378333f5d
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