| #
f8363a8e |
| 17-Oct-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_dtb_console" into integration
* changes:
feat(versal-net): retrieval of console information from dtb
feat(versal): retrieval of console information from dtb
refa
Merge changes from topic "xlnx_dtb_console" into integration
* changes:
feat(versal-net): retrieval of console information from dtb
feat(versal): retrieval of console information from dtb
refactor(xilinx): create generic function for clock retrieval
feat(zynqmp): retrieval of console information from dtb
show more ...
|
| #
a467e813 |
| 20-Sep-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
feat(versal-net): retrieval of console information from dtb
Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.
Comparing early console info
feat(versal-net): retrieval of console information from dtb
Introduces functionality to retrieve console information from the
device tree (DTB) and use it in TF-A code.
Comparing early console information and the data populated from
the DTB. In case of a mistmatch, the changes takes care of
unregistering the build time console configuration and registering the
DTB-based console.
Reorganizes the console configuration setup in BL31 by moving it to a
dedicated function called setup_console() in the plat_console.c
file. This change improves code readability by isolating console-
related settings, making it easier to manage and extend the console
configuration in the future.
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Change-Id: I7b6ebad0e91133ab5fbda8f3a8663abfb6dd2458
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|
| #
4593e7cb |
| 27-Sep-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-crash" into integration
* changes:
feat(xilinx): used console also as crash console
feat(versal-net): remove empty crash console setup
|
| #
6a14246a |
| 18-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): remove empty crash console setup
Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash conso
feat(versal-net): remove empty crash console setup
Private plat_crash_console_init() has all the setup commented
that's why it was never been tested.
pl011 uart is supposed to be used as crash console and it should be
enought to add CONSOLE_FLAG_CRASH and remove platform specific
implementation and use generic one.
Early console can't be used for early ASM debugging but that's
expected and not required.
Change-Id: I1267fd78c0d6532a0baddbcad8a5b2a7dfc7750b
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
b8b1c1f5 |
| 14-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "xlnx_dtb_modification" into integration
* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime
|
| #
46a08aab |
| 10-Jul-2023 |
Amit Nagal <amit.nagal@amd.com> |
feat(versal-net): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build
feat(versal-net): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I45a5d9a8343ea8a19ea014a70023731de94d061a
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| #
16cb3be8 |
| 24-May-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_smcc_soc_id" into integration
* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net):
Merge changes from topic "xlnx_smcc_soc_id" into integration
* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid
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|
| #
32d6396a |
| 24-May-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal-net): add the IPI CRC checksum macro support" into integration
|
| #
1873e7f7 |
| 03-Apr-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): add support for SMCC ARCH SOC ID
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to ob
feat(versal-net): add support for SMCC ARCH SOC ID
Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal NET platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.
Change-Id: I6648051c7f5fa27d2f02080209da36ee8d5a9d95
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| #
ba56b012 |
| 15-May-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
feat(versal-net): add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Sign
feat(versal-net): add the IPI CRC checksum macro support
Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.
Change-Id: I14dee4729f88c407bafdf1d6b46106459d8e22c4
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
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|
| #
d84171b4 |
| 20-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
|
| #
619bc13e |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
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|
| #
523389e7 |
| 28-Mar-2023 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(xilinx): move versal files to common place" into integration
|
| #
a92681d9 |
| 22-Dec-2022 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
refactor(xilinx): move versal files to common place
Moved necessary files to common place so that it can be used for
Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id
refactor(xilinx): move versal files to common place
Moved necessary files to common place so that it can be used for
Versal NET.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I611fa849207b082e6599acfb65c55d27b9c99435
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|
| #
1548e0e7 |
| 02-Feb-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_feat_chores" into integration
* changes:
chore(xilinx): update print information
feat(versal-net): add jtag dcc support
|
| #
30e8bc36 |
| 18-Jan-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC i
feat(versal-net): add jtag dcc support
Add support for JTAG Debug Communication Channel(DCC), using the dcc
console driver, for Versal NET platform.
UART0/UART1 is not configured when the JTAG DCC is used as console for
the platform.
Though DCC is not using any UART, VERSAL_NET_UART_BASE needs
to be defined in the platform code. If its not defined, build errors
are observed.
Now VERSAL_NET_UART_BASE by default points to UART0 base.
Check for valid console(pl011, pl011_0, pl011_1, dcc) is
being done in the platform makefile, the error condition in
setting the value of VERSAL_NET_UART_BASE is redundant, thus the error
message is removed from the code.
Change-Id: I1085433055abea13526230cff4d4183ff7a01477
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| #
caea0965 |
| 16-Jan-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal-net): add support for uart1 console" into integration
|
| #
2f1b4c55 |
| 13-Jan-2023 |
Akshay Belsare <akshay.belsare@amd.com> |
feat(versal-net): add support for uart1 console
Versal NET platform supports two UART(UART0, UART1)
Add support for UART1 to be used as console for Versal NET platform.
Change-Id: I3bc2034f54052e37
feat(versal-net): add support for uart1 console
Versal NET platform supports two UART(UART0, UART1)
Add support for UART1 to be used as console for Versal NET platform.
Change-Id: I3bc2034f54052e37cc480f98d48335fa5b2138bf
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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|
| #
e504ce5f |
| 14-Oct-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal_net): Enable a78 errata workarounds" into integration
|
| #
bcc6e4a0 |
| 11-Oct-2022 |
Akshay Belsare <Akshay.Belsare@amd.com> |
fix(versal_net): Enable a78 errata workarounds
TF-A is reporting that erratum are missing to be enabled.
Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_194
fix(versal_net): Enable a78 errata workarounds
TF-A is reporting that erratum are missing to be enabled.
Enable the Following errata workaround to Cortex-A78 AE CPU for versal_net
ERRATA_A78_AE_1941500
ERRATA_A78_AE_1951502
ERRATA_A78_AE_2376748
ERRATA_A78_AE_2395408
For further information refer to
https://developer.arm.com/documentation/SDEN1707912/1300/
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: Ib7fc16e035feab1dfbd88c1f8ce128b057eee86d
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|
| #
f47d38ba |
| 21-Sep-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP s
Merge changes from topic "xilinx-versal-net" into integration
* changes:
feat(versal-net): add support for platform management
feat(versal-net): add support for IPI
feat(versal-net): add SMP support for Versal NET
feat(versal-net): add support for Xilinx Versal NET platform
feat(versal-net): add documentation for Versal NET SoC
show more ...
|
| #
0654ab7f |
| 05-Sep-2022 |
Jay Buddhabhatti <jay.buddhabhatti@xilinx.com> |
feat(versal-net): add support for platform management
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by
feat(versal-net): add support for platform management
Add support for PM EEMI interface for Versal_net. Also use PM
APIs in psci ops. Added TFA_NO_PM flag to disable PM functionality.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Change-Id: If2b2941c868bc9b0850d7f3adb81eac0e660c149
show more ...
|
| #
0bf622de |
| 19-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add support for IPI
Add support to send IPI to firmware.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd5
feat(versal-net): add support for IPI
Add support to send IPI to firmware.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I8cd54c05b6a726e0d398dfc1cdcc7f4cf09ba725
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|
| #
8529c769 |
| 19-Sep-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add SMP support for Versal NET
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare
feat(versal-net): add SMP support for Versal NET
Add SMP support for Versal NET via register access.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I46d73e2cd678ae720b5255722b6b0611c22659e8
show more ...
|
| #
1d333e69 |
| 31-Aug-2022 |
Michal Simek <michal.simek@amd.com> |
feat(versal-net): add support for Xilinx Versal NET platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx P
feat(versal-net): add support for Xilinx Versal NET platform
New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410
show more ...
|