| fa98d7f2 | 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type.
fix(plat/xilinx/versal): resolve misra R10.6 in pm services
MISRA Violation: MISRA-C:2012 R.10.6
- The value of a composite expression shall not be assigned to an object
with wider essential type.
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I67ac6b6b4b643f57e76a435345540e241c9a88b9
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| 27ae5310 | 05-Aug-2021 |
Abhyuday Godhasara <abhyuday.godhasara@xilinx.com> |
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause
Signed-off-by: Abhyuday Godha
fix(plat/xilinx/versal): resolve misra R16.3 in pm services
MISRA Violation: MISRA-C:2012 R.16.3
- An unconditional break statement shall terminate every switch-clause
Signed-off-by: Abhyuday Godhasara <abhyuday.godhasara@xilinx.com>
Change-Id: I576b2c6eb7d1b7ef20440b9a616886ccf230b63e
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| 78c7beb4 | 31-Mar-2021 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change
plat: send an sgi to communicate to linux
Upon recieving the interrupt send an SGI.
The sgi number is communicated by linux.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Change-Id: Ib8f07ff7132ba5ac202b546914efb16d04820ed3
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
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| 07d8a5f7 | 25-Nov-2020 |
Tejas Patel <tejas.patel@xilinx.com> |
plat: xilinx: versal: Add support of set max latency for the device
Add support of set max latency, to change in the maximum powerup latency
requirements for a specific device currently used by Subs
plat: xilinx: versal: Add support of set max latency for the device
Add support of set max latency, to change in the maximum powerup latency
requirements for a specific device currently used by Subsystem.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I8749886abb1a7884a42c4d156d89c9cd562a5b1a
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| 2cc1fa95 | 12-Aug-2019 |
Ravi Patel <ravi.patel@xilinx.com> |
plat: versal: Add InitFinalize API call
Add support to call InitFinalize API in Versal which calls
corresponding LibPM API.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Va
plat: versal: Add InitFinalize API call
Add support to call InitFinalize API in Versal which calls
corresponding LibPM API.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I3428b7245b4db1ef6db8a90b7ad20b6e484ed3b2
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| 1ba2d84f | 23-Nov-2020 |
Rajan Vaja <rajan.vaja@xilinx.com> |
xilinx: versal: Updated Response of QueryData API call
For the current XilPM calls, The handler of IPI returns information
with 16 Bytes data.
So during QueryData API call for the ClockName and PinF
xilinx: versal: Updated Response of QueryData API call
For the current XilPM calls, The handler of IPI returns information
with 16 Bytes data.
So during QueryData API call for the ClockName and PinFunctionName,
response data(name of clock or function) response[0..3] are used to
return name. And status is not being returned for such API.
Updated XilPM calls reply in a consistent way and The handler of IPI
return information with 32Bytes data. Where response[0] always set
to status.
For the version-2 of QueryData API, during call for the ClockName
and PinFunctionName, response data(name of clock or function) get as
response[1...4].
To support both the version of QueryData API, added version based
compatibility by the use of feature check.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Amit Sunil Dhamne <amit.sunil.dhamne@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I336128bff7bbe659903b0f8ce20ae6da7e3b51b4
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| abf27efa | 23-Nov-2020 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat:xilinx:versal: Use defaults when PDI is without sw partitions
In JTAG mode check the ATF handoff structure, if the magic string
is not present then use bl32 and bl33 default values.
Signed-off
plat:xilinx:versal: Use defaults when PDI is without sw partitions
In JTAG mode check the ATF handoff structure, if the magic string
is not present then use bl32 and bl33 default values.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I1f2c4a2060d8a2e70d3b5fb2473124b685f257fc
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| d4c7b550 | 21-Jun-2019 |
Ravi Patel <ravi.patel@xilinx.com> |
xilinx: versal: Skip store/restore of GIC during CPU idle
GIC registers needs to be stored/restored during system
suspend/resume only and not during CPU idle.
During CPU idle, minimum 1 CPU is in ON
xilinx: versal: Skip store/restore of GIC during CPU idle
GIC registers needs to be stored/restored during system
suspend/resume only and not during CPU idle.
During CPU idle, minimum 1 CPU is in ON state.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I5de2ce3a61bf4260f9385349202b0f592a47aaba
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| 4b8ab607 | 11-Dec-2019 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
plat: versal: Update API list in feature check
Add below API in feature check list which is actually present in
firmware:
- PM_GET_CHIPID
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu
plat: versal: Update API list in feature check
Add below API in feature check list which is actually present in
firmware:
- PM_GET_CHIPID
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Change-Id: I98b82da74164f065c8835861f74b0f2855e9bcbf
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