fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

fix(xilinx): dynamic mmap region for dtb

mmap dtb region before usage and unmap it after usage.
overall size(text,data,bss) of dtb gets reduced by
16 bytes in normal flow and 80 bytes in ddr flow.

Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Change-Id: I411deff57ab141fc2978a2e916aec2d988cb8f9c

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Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net):

Merge changes from topic "xlnx_smcc_soc_id" into integration

* changes:
feat(versal-net): add support for SMCC ARCH SOC ID
feat(versal): add support for SMCC ARCH SOC ID
refactor(versal-net): move macros to common header
feat(xilinx): add support to get chipid

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feat(versal): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the

feat(versal): add support for SMCC ARCH SOC ID

Add support for SMCCC_ARCH_SOC_ID as per SMC Calling Convention for
Versal platform.
The SMCC ARCH SOC ID call is used by system software to obtain the SiP
defined SoC identification details.

Change-Id: I1466a9ad1bc8dde1cda516ddd3edbaa6a5941237
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge changes from topic "versal/xlat-v2" into integration

* changes:
feat(versal): switch to xlat_v2
fix(xilinx): remove asserts around arg0/arg1

Merge "style(xilinx): replace ARM by Arm in copyrights" into integration

feat(versal): switch to xlat_v2

Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.

Change-Id: I3f27591caf944dc758cc45ee870

feat(versal): switch to xlat_v2

Switch to v2 version to add support for dynamic mapping which is not
supported in v1. It can be used for run time DT mapping.

Change-Id: I3f27591caf944dc758cc45ee870b9b5b3ff0a18d
Signed-off-by: Michal Simek <michal.simek@amd.com>

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style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure

style(xilinx): replace ARM by Arm in copyrights

The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.

Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "refactor(xilinx): move versal files to common place" into integration

refactor(xilinx): move versal files to common place

Moved necessary files to common place so that it can be used for
Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id

refactor(xilinx): move versal files to common place

Moved necessary files to common place so that it can be used for
Versal NET.

Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I611fa849207b082e6599acfb65c55d27b9c99435

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Merge "fix(versal): enable a72 erratum 859971 and 1319367" into integration

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https

fix(versal): enable a72 erratum 859971 and 1319367

TF-A is reporting that above two erratum are missing to be enabled that's
why enable them by default.

For futher information please refer to
https://developer.arm.com/documentation/epm012079/11/

where
859971 is "Speculative instruction prefetch to Execute-never (XN) memory
could cause deadlock or data integrity issue" and
1319367 is "Speculative AT instruction using out-of-context translation
regime could cause subsequent request to generate an incorrect
translation".

Change-Id: I408706713a169e53db63ac5657751b0b003e646d
Signed-off-by: Michal Simek <michal.simek@amd.com>

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Merge "feat(plat/versal): add support for SLS mitigation" into integration

feat(plat/versal): add support for SLS mitigation

This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerabili

feat(plat/versal): add support for SLS mitigation

This patch adds the option HARDEN_SLS_ALL that can be used to enable
the -mharden-sls=all, which mitigates the straight-line speculation
vulnerability. Enable this by adding the option HARDEN_SLS_ALL=1,
default this will be disabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I0d498d9e96903fcb879993ad491949f6f17769b2

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Merge changes I3c25c715,I6d30b081 into integration

* changes:
plat: xilinx: versal: Add the IPI CRC checksum macro support
plat: xilinx: common: Rename the IPI CRC checksum macro

plat: xilinx: versal: Add the IPI CRC checksum macro support

Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.ab

plat: xilinx: versal: Add the IPI CRC checksum macro support

Add support for CRC checksum for IPI data when the macro
IPI_CRC_CHECK is enabled.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I3c25c715885759076055c6505471339b5d6edcd5

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Merge changes from topic "dcc_console" into integration

* changes:
plat:xilinx:versal: Add JTAG DCC support
plat:xilinx:zynqmp: Add JTAG DCC support
drivers: dcc: Support JTAG DCC console

plat:xilinx:versal: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Mic

plat:xilinx:versal: Add JTAG DCC support

As per the new multi-console framework, updating the JTAG DCC support.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I77994ce387caf0d695986df3d01d414a920978d0

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Merge "plat: xilinx: versal: Remove cortex-a53 compilation" into integration

plat: xilinx: versal: Remove cortex-a53 compilation

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

plat: xilinx: versal: Remove cortex-a53 compilation

Versal is a72 based that's why there is no reason to build low level
assemble code for a53.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: Iff9cf2582102d951825b87fd9af18e831ca717d6

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Merge "TF-A GICv3 driver: Introduce makefile" into integration

TF-A GICv3 driver: Introduce makefile

This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affectin

TF-A GICv3 driver: Introduce makefile

This patch moves all GICv3 driver files into new added
'gicv3.mk' makefile for the benefit of the generic driver
which can evolve in the future without affecting platforms.
The patch adds GICv3 driver configuration flags
'GICV3_IMPL', 'GICV3_IMPL_GIC600_MULTICHIP' and
'GICV3_OVERRIDE_DISTIF_PWR_OPS' described in
'GICv3 driver options' section of 'build-option.rst'
document.

NOTE: Platforms with GICv3 driver need to be modified to
include 'drivers/arm/gic/v3/gicv3.mk' in their makefiles.

Change-Id: If055f6770ff20f5dee5a3c99ae7ced7cdcac5c44
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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Merge "TF-A GICv3 driver: Separate GICD and GICR accessor functions" into integration

TF-A GICv3 driver: Separate GICD and GICR accessor functions

This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3

TF-A GICv3 driver: Separate GICD and GICR accessor functions

This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.

Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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