| #
5ee0b385 |
| 13-Aug-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_misra_fix_versal" into integration
* changes:
fix(versal): match function type as its declared
fix(versal): switch case has only one confirming clause
fix(versal
Merge changes from topic "xlnx_misra_fix_versal" into integration
* changes:
fix(versal): match function type as its declared
fix(versal): switch case has only one confirming clause
fix(versal): typecast operands to match data type
fix(versal): replace ull with ULL to fix misra violation
fix(versal): typecast operands to match data type
fix(versal): match function declaration with its definition
fix(versal): add external declaration
show more ...
|
| #
33a264cb |
| 27-Jan-2025 |
Saivardhan Thatikonda <saivardhan.thatikonda@amd.com> |
fix(versal): add external declaration
This corrects the MISRA violation C2012-8.4:
A compatible declaration shall be visible when an object or
function with external linkage is defined. In this case
fix(versal): add external declaration
This corrects the MISRA violation C2012-8.4:
A compatible declaration shall be visible when an object or
function with external linkage is defined. In this case
function declaration is available in "platform.h".
Change-Id: Ia493b18e563f4d89dc3cbde791aece3c101360ba
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>
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|
| #
d84171b4 |
| 20-Apr-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "style(xilinx): replace ARM by Arm in copyrights" into integration
|
| #
619bc13e |
| 14-Apr-2023 |
Michal Simek <michal.simek@amd.com> |
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure
style(xilinx): replace ARM by Arm in copyrights
The commit 6bb49c876c75 ("style(hooks): adds Arm copyright style fix")
is enforcing proper case for ARM. That's why fix it in plat/xilinx to
make sure that pre-commit.copyright won't be touching platform specific
files.
Change-Id: I49c66e18d46ed871a6aa128c9b2a403d0cf83416
Signed-off-by: Michal Simek <michal.simek@amd.com>
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|
| #
40366cb6 |
| 24-Jun-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "xlnx_versal_misra_fix" into integration
* changes:
fix(versal): resolve misra 15.6 warnings
fix(zynqmp): resolve misra 8.13 warnings
fix(versal): resolve misra 8.13 w
Merge changes from topic "xlnx_versal_misra_fix" into integration
* changes:
fix(versal): resolve misra 15.6 warnings
fix(zynqmp): resolve misra 8.13 warnings
fix(versal): resolve misra 8.13 warnings
fix(versal): resolve the misra 4.6 warnings
show more ...
|
| #
912b7a6f |
| 24-May-2022 |
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> |
fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by:
fix(versal): resolve the misra 4.6 warnings
MISRA Violation: MISRA-C:2012 R.4.6
- Using basic numerical type int rather than a typedef
that includes size and signedness information.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I4eccce7e238f283348a5013e2e45c91435b4ae4e
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| #
e07666de |
| 12-Nov-2018 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1605 from sivadur/integration
Add support new Xilinx Versal ACAP platform
|
| #
f91c3cb1 |
| 25-Sep-2018 |
Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> |
arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Sc
arm64: versal: Add support for new Xilinx Versal ACAPs
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
leading-edge memory and interfacing technologies to deliver powerful
heterogeneous acceleration for any application. The Versal AI Core series has
five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
optimized for high-precision floating point with low latency.
This patch adds Virtual QEMU platform support for
this SoC "versal_virt".
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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|