Merge changes from topic "xlnx_fix_plat_ns_entry" into integration

* changes:
feat(versal2): validate non-secure entry addr
feat(versal2): parse reserve memory subnodes

feat(versal2): parse reserve memory subnodes

In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point

feat(versal2): parse reserve memory subnodes

In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point address during a hot plug event

Change-Id: I8cdb098509bd3b06f0df5ea647220bdbb8a4bf35
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refacto

Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration

* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refactor console to support transfer list
chore(xilinx): propagate error code
feat(versal2): retrieve DT address from transfer list
chore(versal2): move xfer-list file paths
fix(versal2): update transfer list as optional

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feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44

feat(versal2): retrieve DT address from transfer list

On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.

Change-Id: I44b9a0753809652f26bc1b7e061f5364229ba352
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image ch

Merge changes from topic "xlnx_fitimage_check" into integration

* changes:
fix(xilinx): update correct return types
fix(xilinx): add FIT image check in DT console
fix(xilinx): add FIT image check in prepare_dtb

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fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the pr

fix(xilinx): add FIT image check in prepare_dtb

Introduce two new functions: 'is_valid_image()' and 'is_fit_image()'
to enhance the functionality of the system. 'is_valid_image()' will
verify the presence of the FDT header and ensure that the FDT is
open. Meanwhile, 'is_fit_image()' will be responsible for detecting
FIT images. When TF-A is built with a DTB address during compilation
and later executed from DDR memory, TF-A will dynamically reserve a
memory location in the DTB during runtime.

This approach is effective when a raw DTB is present at the specified
address location. With this change, the "is_fit_image()" function
has been introduced to verify the existence of the "/configurations"
property within the DTB.

The presence of this property is exclusive to FIT images. In case
the property is found, a warning message is displayed, and memory
space reservation for its address space in DDR is not performed by
TF-A. However, if the property is not present, TF-A continues its
usual procedure of updating the raw DTB.

Additionally, dynamic mapping has been refactored and separated into
distinct functions: "add_mmap_dynamic_region ()" and
"remove_dynamic_mmap()". This separation enhances compatibility
and maintains better code organization.

Change-Id: I9cd3f09863b44483445e58c802dee34d58dfe2e9
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge changes from topic "xlnx_dtb_modification" into integration

* changes:
feat(versal-net): ddr address reservation in dtb at runtime
feat(versal): ddr address reservation in dtb at runtime

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build tim

feat(versal): ddr address reservation in dtb at runtime

When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.

A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.

Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.

Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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