fix(ti): align static device region addresses to reduce MMU table count

Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a s

fix(ti): align static device region addresses to reduce MMU table count

Align our device memory regions to the next highest MMU table level (LV2).
This allows the xlat_tables library code to use a single entry in the
higher order table, vs having to create a new table for LV3 entries.

This reduces our tables to just 4: 2 LV2 and 1 LV3 plus 1 spare in case
alignment changes ever cause one to be split. This saves 24KB of our
128KB total TF-A SRAM (~18%!).

While here, as USE_COHERENT_MEM does not change MAX_XLAT_TABLES but
does change our total MAX_MMAP_REGIONS, move that check accordingly.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I4cb8e3b2cc3d05c6c9a84d887dd6ec56bde7a786

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fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xf

fix(ti): fix TISCI API changes during refactor

The refactor caused many APIs to be regressed due to copy paste changes
so fix them.

Fixes: 6688fd7aec2f ("refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response")
Change-Id: I03a808fa0bf2cbefbc1c9924bdaf4cfb2ad7f2cb
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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fix(ti): remove check for zero value in BL31 boot args

The commit 3e14df6f6330 removed clearing of argument registers even when
BL31 is the first stage. In that case the registers are left in a rand

fix(ti): remove check for zero value in BL31 boot args

The commit 3e14df6f6330 removed clearing of argument registers even when
BL31 is the first stage. In that case the registers are left in a random
state. TI platforms check that the arguments have been zero'd in early
setup and so all TI platforms are not broken. Not sure why this check was
here at all, so simply remove it to fix boot.

Fixes: 3e14df6f6330 ("fix(bl31): avoid clearing of argument registers in RESET_TO_BL31 case")
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I02bdd16b67fb5facc4c47ec596a42f110a663377

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feat(ti): synchronize access to secure proxy threads

When communicating with the system controller over secure proxy we clear
a thread, write our message, then wait for a response. This must not be

feat(ti): synchronize access to secure proxy threads

When communicating with the system controller over secure proxy we clear
a thread, write our message, then wait for a response. This must not be
interrupted by a different transfer on the same thread. Take a lock
during this sequence to prevent contention.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I7789f017fde7180ab6b4ac07458464b967c8e580

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refactor(ti): remove inline directive from ti_sci and sec_proxy drivers

Let the compiler choose when to inline. Here this reduces binary size.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6

refactor(ti): remove inline directive from ti_sci and sec_proxy drivers

Let the compiler choose when to inline. Here this reduces binary size.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I68cd0fc3a94c8c94781ca3dc277a1dd4c6f2bd3a

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refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response

This allows us to use the common xfer setup path even for no-wait
messages. Then factor that out of each no-wait function.

refactor(ti): refactor ti_sci_{setup,do}_xfer to allow zero size response

This allows us to use the common xfer setup path even for no-wait
messages. Then factor that out of each no-wait function.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ib17d3facd293f3fc91dda56b2906121b43250261

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feat(ti): add sub and patch version number support

Although we do not use these for anything today, they are returned
in this structure and the struct's definition should match.

While here fix a co

feat(ti): add sub and patch version number support

Although we do not use these for anything today, they are returned
in this structure and the struct's definition should match.

While here fix a couple comment typos.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Iac4ec999b44e703e600bde93b0eee83753566876

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fix(ti): do not take system power reference in bl31_platform_setup()

Taking a reference at this early stage can cause boot failure if the DM
firmware is not fully initialized. Remove this early call

fix(ti): do not take system power reference in bl31_platform_setup()

Taking a reference at this early stage can cause boot failure if the DM
firmware is not fully initialized. Remove this early call until the
fix in DM firmware is widely available.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic9c47ccf1e9a1b9faeb1c7d2665d54cf55ef5396

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build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section name

build: always prefix section names with `.`

Some of our specialized sections are not prefixed with the conventional
period. The compiler uses input section names to derive certain other
section names (e.g. `.rela.text`, `.relacpu_ops`), and these can be
difficult to select in linker scripts when there is a lack of a
delimiter.

This change introduces the period prefix to all specialized section
names.

BREAKING-CHANGE: All input and output linker section names have been
prefixed with the period character, e.g. `cpu_ops` -> `.cpu_ops`.

Change-Id: I51c13c5266d5975fbd944ef4961328e72f82fc1c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(ti): fix typo in boot authentication message name

Fix AUTH_BOOT message identifier (s/IMIAGE/IMAGE).

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Andrew Davis <afd@ti.co

fix(ti): fix typo in boot authentication message name

Fix AUTH_BOOT message identifier (s/IMIAGE/IMAGE).

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I19eb1798c6b9dd8c3f59e05c59318c9c3be971a0

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refactor(ti): remove empty validate_ns_entrypoint function

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I93165e9f26f5a5b600e7b6a9d48df75d62e89f17

refactor(ti): use console_set_scope() rather than empty function hack

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I62c1215bc02e95a7ea9fa1e2dfa9ef05e204fce1

refactor(ti): factor out common board code into common files

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ibf7328418c5285a64608b80e7c430a8dee64fb1d

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c9f200b3d

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feat(ti): do not handle EAs in EL3

This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.

Signed-o

feat(ti): do not handle EAs in EL3

This could be useful if we had extra information to print or
when RAS extensions are available, neither apply here so lets
not trap these in EL3 for now.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ia0334eb845686964e794afe45c7777ea64fd6b0b

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feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by

feat(ti): set snoop-delayed exclusive handling on A72 cores

Snoop requests should not be responded to during atomic operations. This
can be handled by the interconnect using its global monitor or by the
core's SCU delaying to check for the corresponding atomic monitor state.

TI SoCs take the second approach. Set the snoop-delayed exclusive handling
bit to inform the core it needs to delay responses to perform this check.

As J784s4 is currently the only SoC with multiple A72 clusters, limit
this delay to only that device.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I875f64e4f53d47a9a0ccbf3415edc565be7f84d9

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feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49

feat(ti): disable L2 dataless UniqueClean evictions

Do this early before we enable caching as a workaround for ARM A72
Errata #854172.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ic878fdb49e598da0ea6ade012712f8f57023678e

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feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change

feat(ti): set L2 cache ECC and and parity on A72 cores

The Cortex-A72 based cores on K3 platforms have cache ECC and
parity protection, enable these.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c

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feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 acce

feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883

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fix(ras): restrict RAS support for NS world

Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To

fix(ras): restrict RAS support for NS world

Current RAS framework in TF-A only supports handling errors originating
from NS world but the HANDLE_EA_EL3_FIRST flag configures it for all
lower Els. To make the current design of RAS explicit, rename this macro
to HANDLE_EA_EL3_FIRST_NS and set EA bit in scr_el3 only when
switching to NS world.

Note: I am unaware of any platform which traps errors originating in
Secure world to EL3, if there is any such platform then it need to
be explicitly implemented in TF-A

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: If58eb201d8fa792c16325c85c26056e9b409b750

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feat(ti-k3): add support for J784S4 SoCs

The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration

feat(ti-k3): add support for J784S4 SoCs

The J784S4 SoC has two quad Cortex-A72 core clusters. This is the first
SoC in the K3 family with Quad cores in a A-72 cluster. So, a new board
configuration is introduced to support quad core clusters on the J784S4
SoC of the K3 family of devices.

See J784S4 Technical Reference Manual (SPRUJ52 - JUNE 2022)
for further details: http://www.ti.com/lit/zip/spruj52

Signed-off-by: Hari Nagalla <hnagalla@ti.com>
Change-Id: I0ed1f14ab32a56ae06e3df3161ace4597d14a48d

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feat(ti): allow build config of low power mode support

Not all K3 platforms support low power mode, so to allow these
features to be included for platforms that do in build and
therefore reported in

feat(ti): allow build config of low power mode support

Not all K3 platforms support low power mode, so to allow these
features to be included for platforms that do in build and
therefore reported in the PSCI caps, define K3_PM_SYSTEM_SUSPEND
flag that can be set during build that will cause appropriate
space and functionality to be included in build for system
suspend support.

Change-Id: I821fbbd5232d91de6c40f63254b855e285d9b3e8
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Ge

feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): add PSCI handlers for system suspend

Add necessary K3 PSCI handlers to enable system suspend to be reported
in the PSCI capabilities when asked during OS boot.

Additionally, have the hand

feat(ti): add PSCI handlers for system suspend

Add necessary K3 PSCI handlers to enable system suspend to be reported
in the PSCI capabilities when asked during OS boot.

Additionally, have the handlers provide information that all domains
should be off and also have the power domain suspend handler invoke the
TISCI_MSG_ENTER_SLEEP message to enter system suspend.

Change-Id: I351a16167770e9909e8ca525ee0d74fa93331194
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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feat(ti): add gic save and restore calls

Add functions to save and restore GICv3 redist and dist contexts during
low power mode and then call these during the suspend entry and finish
psci handlers.

feat(ti): add gic save and restore calls

Add functions to save and restore GICv3 redist and dist contexts during
low power mode and then call these during the suspend entry and finish
psci handlers.

Change-Id: I26c2c0f3b7fc925de3b349499fa42d2405441577
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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