fix(k3low): extend BL1 RW region for debug builds

DEBUG=1 builds include larger xlat tables that overflow BL1's 12K RW
region by 4K. Extend BL1_RW_LIMIT by 0x1000 under #ifdef DEBUG and
emit a loud

fix(k3low): extend BL1 RW region for debug builds

DEBUG=1 builds include larger xlat tables that overflow BL1's 12K RW
region by 4K. Extend BL1_RW_LIMIT by 0x1000 under #ifdef DEBUG and
emit a loud make-time warning that this binary is non-functional
(the extended region overlaps MAILBOX_SHMEM).
Also, add an ERROR print to make sure users are aware at boot
that BL1 has been built with DEBUG flag and panic.

NOT intended for production or functional testing.

Change-Id: Iae9453d8c5305e3e88c6e21fa5ac042c9a210d37
Co-developed-by: Claude <noreply@anthropic.com>
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(k3low): add BL1 platform definitions and integration for AM62L

AM62L devices use BL1 to configure DDR4/LPDDR4 before the secondary
bootloader. This patch wires all prior DDR and board patches i

feat(k3low): add BL1 platform definitions and integration for AM62L

AM62L devices use BL1 to configure DDR4/LPDDR4 before the secondary
bootloader. This patch wires all prior DDR and board patches into a
complete, buildable bl1.bin:

- ti_platform_defs.h: add IMAGE_BL1 conditionals for BL1-specific
stack and memory layout definitions.
- platform_def.h: add BL1 SRAM base/size and mailbox address
definitions used by am62l_bl1_setup.c.
- am62l_bl1_setup.c: BL1 platform initialisation — console, DDR
init via the Cadence/TI shim, and WFI-based handoff to the
secondary bootloader.
- platform.mk: add BL1_SOURCES, K3_LPDDR4_SOURCES, update BUILD_PLAT
and PLAT_INCLUDES to compile all DDR and BL1 sources.

Change-Id: I91e8b9e8e43a5560aa688d58e6805a7b5236de44
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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feat(k3low): add AM62L DDR platform shim and EVM board config

Rename the board directory from am62lx/ to am62lx-evm/ to reflect the
specific board variant, and introduce the EVM board configuration:

feat(k3low): add AM62L DDR platform shim and EVM board config

Rename the board directory from am62lx/ to am62lx-evm/ to reflect the
specific board variant, and introduce the EVM board configuration:

- board_config.c: pad-mux initialisation for MAIN/WKUP UART0 pins,
verified against the AM62L TRM (SPRUJB4A p.3976).
- board_def.h: board-level UART base and clock definitions.
- board_config.h: shared header declaring board_init().

Add the TI-authored AM62L DDRSS platform shim that wraps the Cadence
driver for this SoC:

- am62l_ddrss.c / am62l_ddrss.h: PSC power sequencing and DDR
initialisation flow calling the Cadence CTL/PHY/PI APIs.
- am62lx_ddr_config.c / am62lx_ddr_config.h: register data for the
AM62L DDRSS configuration.
- am62lx_skevm_lp4_50_800.h: machine-generated SK-EVM LPDDR4 register
values produced by the SysConfig DDR tool v0.10.30. This file should
be regenerated via that tool if board or timing parameters change.

New source files are intentionally unreferenced in platform.mk pending
the BL1 integration patch.

board.mk is introduced as a placeholder required by platform.mk's
include directive for BL31 builds; BL1_SOURCES will be added in the
next patch when BL1 support is wired in.

Change-Id: I8aff5eb1c2429646a701dc3b09821318bb6e73b9
Signed-off-by: Hari Nagalla <hnagalla@ti.com>

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feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware b

feat(ti): add mmu regions for am62l soc

Update the k3low bl31 platform setup to map required device regions
(USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all
necessary hardware blocks are accessible to the A53 cores on the
AM62L SoC.
Use 4K aligned address sizes wherever applicable, and update the
file header comment from "K3 SOC specific bl31_setup" to "k3low SoC
specific bl31_setup" to accurately represent the platform specific
nature of this file.
As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE
to WKUP_CTRL_MMR0_BASE to make name shorter.

Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some high

feat(ti): introduce basic support for the AM62L

The AM62L is a lite, low power and performance optimized family of
application processors that are built for Linux application development.

Some highlights of AM62L SoC are:
- Single to Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem
- 16-bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
- Multiple low power modes support, ex: Deep sleep and RTC+DDR
- Mailbox transport layer for TI SCI

For more information check out our Technical Reference Manual (TRM)
which is loacted here:

https://www.ti.com/lit/pdf/sprujb4

Change-Id: I9d7c707b5b220c5ec13bd2de67f872b3da3c308a
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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