| 8853eba6 | 05-Jun-2025 |
Dhruva Gole <d-gole@ti.com> |
feat(ti): add mmu regions for am62l soc
Update the k3low bl31 platform setup to map required device regions (USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all necessary hardware b
feat(ti): add mmu regions for am62l soc
Update the k3low bl31 platform setup to map required device regions (USART, GIC, GTC, MMR, and mailbox) in the MMU. This ensures that all necessary hardware blocks are accessible to the A53 cores on the AM62L SoC. Use 4K aligned address sizes wherever applicable, and update the file header comment from "K3 SOC specific bl31_setup" to "k3low SoC specific bl31_setup" to accurately represent the platform specific nature of this file. As part of the effort, rename WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE to WKUP_CTRL_MMR0_BASE to make name shorter.
Change-Id: I58209bc9c780db3e452b09c2c939bb0c47a63ed1 Signed-off-by: Dhruva Gole <d-gole@ti.com>
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| 21b14fd2 | 11-Dec-2024 |
Dhruva Gole <d-gole@ti.com> |
feat(ti): introduce basic support for the AM62L
The AM62L is a lite, low power and performance optimized family of application processors that are built for Linux application development.
Some high
feat(ti): introduce basic support for the AM62L
The AM62L is a lite, low power and performance optimized family of application processors that are built for Linux application development.
Some highlights of AM62L SoC are: - Single to Dual 64-bit Arm® Cortex®-A53 microprocessor subsystem - 16-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. - Multiple low power modes support, ex: Deep sleep and RTC+DDR - Mailbox transport layer for TI SCI
For more information check out our Technical Reference Manual (TRM) which is loacted here:
https://www.ti.com/lit/pdf/sprujb4
Change-Id: I9d7c707b5b220c5ec13bd2de67f872b3da3c308a Signed-off-by: Dhruva Gole <d-gole@ti.com>
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