TF-A GICv3 driver: Separate GICD and GICR accessor functions

This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3

TF-A GICv3 driver: Separate GICD and GICR accessor functions

This patch provides separation of GICD, GICR accessor
functions and adds new macros for GICv3 registers access
as a preparation for GICv3.1 and GICv4 support.
NOTE: Platforms need to modify to include both
'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the
single helper file previously.

Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

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16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data stru

16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "Use correct type when reading SCR register" into integration

Use correct type when reading SCR register

The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b6

Use correct type when reading SCR register

The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

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ti: k3: drivers: ti_sci: Put sequence number in coherent memory

The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so ac

ti: k3: drivers: ti_sci: Put sequence number in coherent memory

The current message sequence number is accessed both with caches on and
off so put this memory in the un-cached coherent section so accesses
are consistent and coherency is maintained.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807

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ti: k3: drivers: ti_sci: Remove indirect structure of const data

The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
str

ti: k3: drivers: ti_sci: Remove indirect structure of const data

The 'info' structure contained what is only static data for this
implementation of TI-SCI. Remove this indirection and remove the
struct.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072

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ti: k3: common: Enable ARM cluster power down

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sendi

ti: k3: common: Enable ARM cluster power down

When all cores in a cluster are powered down the parent cluster can
be also powered down. When the last core has requested powering down
follow by sending the cluster power down sequence to the system
power controller firmware.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216

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ti: k3: common: Rename device IDs to be more consistent

The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.

ti: k3: common: Rename device IDs to be more consistent

The core number is called 'core_id' but the processor and device IDs are
called 'proc' and 'device'. Rename these to make them less confusing.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59

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ti: k3: common: Add PIE support

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.

ti: k3: common: Add PIE support

Running TF-A from non-standard location such as DRAM is useful for some
SRAM heavy use-cases. Allow the TF-A binary to be executed from an
arbitrary memory location.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111

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ti: k3: common: Trap all asynchronous bus errors to EL3

These errors are asynchronous and cannot be directly correlated with the
exact current running software, so handling them in the same EL is no

ti: k3: common: Trap all asynchronous bus errors to EL3

These errors are asynchronous and cannot be directly correlated with the
exact current running software, so handling them in the same EL is not
critical. Handling them in TF-A allows for more platform specific
decoding of the implementation defined exception registers

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda

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Remove MULTI_CONSOLE_API flag and references to it

The new API becomes the default one.

Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.co

Remove MULTI_CONSOLE_API flag and references to it

The new API becomes the default one.

Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

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ti: k3: common: Remove coherency workaround for AM65x

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the las

ti: k3: common: Remove coherency workaround for AM65x

We previously left our caches on during power-down to prevent any
non-caching accesses to memory that is cached by other cores. Now with
the last accessed areas all being marked as non-cached by
USE_COHERENT_MEM we can rely on that to workaround our interconnect
issues. Remove the old workaround.

Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7
Signed-off-by: Andrew F. Davis <afd@ti.com>

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ti: k3: common: Use coherent memory for shared data

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets

ti: k3: common: Use coherent memory for shared data

HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.

For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.

Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>

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ti: k3: common: Set L2 latency on A72 cores

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency h

ti: k3: common: Set L2 latency on A72 cores

The Cortex-A72 based cores on K3 platforms can be clocked fast
enough that an extra latency cycle is needed to ensure correct
L2 access. Set the latency here for all A72 cores.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id534316dec1c1f326908efbfd964f219cda7386a

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ti: k3: common: Add support for J721E

Enable Cortex-A72 support for J721E.

Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Da

ti: k3: common: Add support for J721E

Enable Cortex-A72 support for J721E.

Change-Id: I5bea5fb6ec45d1a9f8f2192d42da2cc03ae0f7ec
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Andrew F. Davis <afd@ti.com>

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ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by d

ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by defined the number of cores on that port to zero.
This simplifies several code paths, do this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a

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ti: k3: common: Mark sections for AM65x coherency workaround

These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is no

ti: k3: common: Mark sections for AM65x coherency workaround

These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is not either. Mark it off to keep it separated from the rest of
the PSCI implementation.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I113ca6a2a1f7881814ab0a64e5bac57139bc03ef

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ti: k3: common: Allow USE_COHERENT_MEM for K3

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.

Signed-off-by: An

ti: k3: common: Allow USE_COHERENT_MEM for K3

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I1c05477a97646ac73846a711bc38d3746628d847

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ti: k3: common: Fix RO data area size calculation

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

ti: k3: common: Fix RO data area size calculation

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

Note, this was noticed at a glance thanks to the new aligned formating
of this table.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7

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ti: k3: common: Remove unused STUB macro

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Cha

ti: k3: common: Remove unused STUB macro

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ida33f92fe3810a89e6e51faf6e93c1d2ada1a2ee

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Merge changes from topic "k3-sequence-fix" into integration

* changes:
ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID
ti: k3: drivers: ti_sci: Cleanup sequence ID usage
ti:

Merge changes from topic "k3-sequence-fix" into integration

* changes:
ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID
ti: k3: drivers: ti_sci: Cleanup sequence ID usage
ti: k3: drivers: sec_proxy: Use direction definitions
ti: k3: drivers: sec_proxy: Fix printf format specifiers

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ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID

When we get a sequence ID that does not match what we expect then the we
are looking at is not the one we are expecting and so we er

ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID

When we get a sequence ID that does not match what we expect then the we
are looking at is not the one we are expecting and so we error out. We
can also assume this message is a stale message left in the queue, in
this case we can read in the next message and check again for our
message. Switch to doing that here. We only retry a set number of times
so we don't lock the system if our message is actually lost and will
never show up.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c

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ti: k3: drivers: ti_sci: Cleanup sequence ID usage

The sequence ID can be set with a message to identify it when it is
responded to in the response queue. We assign each message a number and
check f

ti: k3: drivers: ti_sci: Cleanup sequence ID usage

The sequence ID can be set with a message to identify it when it is
responded to in the response queue. We assign each message a number and
check for this same number to detect response mismatches.

Start this at 0 and increase it by one for each message sent, even ones
that do not request or wait for a response as one may still be delivered
in some cases and we want to detect this.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea

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ti: k3: drivers: sec_proxy: Use direction definitions

The direction of a thread should be explicitly compared to avoid
confusion. Also fixup message wording based on this direction.

Signed-off-by:

ti: k3: drivers: sec_proxy: Use direction definitions

The direction of a thread should be explicitly compared to avoid
confusion. Also fixup message wording based on this direction.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11

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ti: k3: drivers: sec_proxy: Fix printf format specifiers

The ID of a thread is not used outside for printing it out when
something goes wrong. The specifier used is also not consistent.
Instead of s

ti: k3: drivers: sec_proxy: Fix printf format specifiers

The ID of a thread is not used outside for printing it out when
something goes wrong. The specifier used is also not consistent.
Instead of storing the thread ID, store its name and print that.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b

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