Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function

Merge changes from topic "ti-k3-checks-and-refactor" into integration

* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function
refactor(ti): use console_set_scope() rather than empty function hack
refactor(ti): factor out common board code into common files
feat(ti): add PSCI system_off support
feat(ti): do not handle EAs in EL3
feat(ti): set snoop-delayed exclusive handling on A72 cores
feat(ti): disable L2 dataless UniqueClean evictions
feat(ti): set L2 cache ECC and and parity on A72 cores
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles

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refactor(ti): factor out common board code into common files

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: Ibf7328418c5285a64608b80e7c430a8dee64fb1d

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c

feat(ti): add PSCI system_off support

Send a TI-SCI control message to system firmware to power down the board.

Signed-off-by: Andrew Davis <afd@ti.com>
Change-Id: I6b8fa64baa94da078db82fc8e115630c9f200b3d

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Merge changes from topic "ti-k3-system-suspend-base-support" into integration

* changes:
feat(ti): allow build config of low power mode support
feat(ti): increase SEC_SRAM_SIZE to 128k
feat(ti

Merge changes from topic "ti-k3-system-suspend-base-support" into integration

* changes:
feat(ti): allow build config of low power mode support
feat(ti): increase SEC_SRAM_SIZE to 128k
feat(ti): add PSCI handlers for system suspend
feat(ti): add gic save and restore calls
feat(ti): add enter sleep method

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feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Ge

feat(ti): increase SEC_SRAM_SIZE to 128k

Increase the lite platform SEC_SRAM_SIZE to 128k to allow space
for GIC context.

Change-Id: I6414309757ce9a9b7b3a9233a401312bfc459a3b
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

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Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our ma

Merge changes I8e67a921,I0dc06072,I5e149063,I962cdfc7,I5c5d0444 into integration

* changes:
plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0
plat: ti: k3: board: Lets cast our macros
plat: ti: k3: common: bl31_setup: Use BL31_SIZE instead of computing
plat: ti: k3: platform_def.h: Define the correct number of max table entries
plat: ti: k3: board: lite: Increase SRAM size to account for additional table

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plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0

ENABLE_PIE (position independent executable) is default on K3
platform to handle variant RAM configurations in the system. This,
unfo

plat: ti: k3: board: Let explicitly map our SEC_SRAM_BASE to 0x0

ENABLE_PIE (position independent executable) is default on K3
platform to handle variant RAM configurations in the system. This,
unfortunately does cause confusion while reading the code, so, lets
make things explicit by selecting 0x0 as the "SEC_SRAM_BASE" out of
which we compute the BL31_BASE depending on usage.

Lets also document a warning while at it to help folks copying code
over to a custom K3 platform and optimizing size by disabling PIE to
modify the defaults.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8e67a9210e907e266ff6a78ba4d02e3259bb2b21

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plat: ti: k3: board: Lets cast our macros

Lets cast our macros to the right types and reduce a few MISRA
warnings.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I0dc06072713fe7c9440eca063509

plat: ti: k3: board: Lets cast our macros

Lets cast our macros to the right types and reduce a few MISRA
warnings.

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I0dc06072713fe7c9440eca0635094c5f3ceb7f1c

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plat: ti: k3: board: lite: Increase SRAM size to account for additional table

We actually have additional table entries than what we accounted for in
our size. MAX_XLAT_TABLES is 8, but really we co

plat: ti: k3: board: lite: Increase SRAM size to account for additional table

We actually have additional table entries than what we accounted for in
our size. MAX_XLAT_TABLES is 8, but really we could be using upto 10
depending on the platform. So, we need an extra 8K space in.

This gets exposed with DEBUG=1 and assert checks trigger, which for some
reason completely escaped testing previously.

ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:97
BACKTRACE: START: assert

Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I5c5d04440ef1fccfaf2317066f3abbc0ec645903

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Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration

* changes:
ti: k3: Introduce lite device board support
ti: k3: common: sec_proxy: Introduce sec_proxy_lite d

Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration

* changes:
ti: k3: Introduce lite device board support
ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition
ti: k3: Move USE_COHERENT_MEM only for the generic board
ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain
ti: k3: common: sec_proxy: Fill non-message data fields with 0x0
ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg
ti: k3: common: Enable A72 erratum 1319367
ti: k3: common: Enable A53 erratum 1530924
maintainers: Update maintainers for TI port

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ti: k3: Introduce lite device board support

Add device support for the 'lite' K3 devices. These will use modified
device addresses and allow for fewer cores to save memory.

Note: This family of dev

ti: k3: Introduce lite device board support

Add device support for the 'lite' K3 devices. These will use modified
device addresses and allow for fewer cores to save memory.

Note: This family of devices are characterized by a single cluster
of ARMv8 processor upto a max of 4 processors and lack of a level 3
cache.

The first generation of this family is introduced with AM642.

See AM64X Technical Reference Manual (SPRUIM2, Nov 2020)
for further details: https://www.ti.com/lit/pdf/spruim2

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Change-Id: I8cd2c1c9a9434646d0c72fca3162dd5bc9bd692a

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