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01855239 |
| 16-Jan-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "ti-k3-checks-and-refactor" into integration
* changes: fix(ti): fix typo in boot authentication message name refactor(ti): remove empty validate_ns_entrypoint function
Merge changes from topic "ti-k3-checks-and-refactor" into integration
* changes: fix(ti): fix typo in boot authentication message name refactor(ti): remove empty validate_ns_entrypoint function refactor(ti): use console_set_scope() rather than empty function hack refactor(ti): factor out common board code into common files feat(ti): add PSCI system_off support feat(ti): do not handle EAs in EL3 feat(ti): set snoop-delayed exclusive handling on A72 cores feat(ti): disable L2 dataless UniqueClean evictions feat(ti): set L2 cache ECC and and parity on A72 cores feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
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| #
c390ecd6 |
| 23-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration
* changes: ti: k3: Introduce lite device board support ti: k3: common: sec_proxy: Introduce sec_proxy_lite d
Merge changes I8cd2c1c9,I697711ee,I4a0ec150,I4f8064b9,Ie22cb2a3, ... into integration
* changes: ti: k3: Introduce lite device board support ti: k3: common: sec_proxy: Introduce sec_proxy_lite definition ti: k3: Move USE_COHERENT_MEM only for the generic board ti: k3: drivers: ti_sci: Update ti_sci_msg_req_reboot to include domain ti: k3: common: sec_proxy: Fill non-message data fields with 0x0 ti: k3: common: Make plat_get_syscnt_freq2 check CNT_FID0 GTC reg ti: k3: common: Enable A72 erratum 1319367 ti: k3: common: Enable A53 erratum 1530924 maintainers: Update maintainers for TI port
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| #
84af8956 |
| 09-Dec-2020 |
Andrew F. Davis <afd@ti.com> |
ti: k3: Introduce lite device board support
Add device support for the 'lite' K3 devices. These will use modified device addresses and allow for fewer cores to save memory.
Note: This family of dev
ti: k3: Introduce lite device board support
Add device support for the 'lite' K3 devices. These will use modified device addresses and allow for fewer cores to save memory.
Note: This family of devices are characterized by a single cluster of ARMv8 processor upto a max of 4 processors and lack of a level 3 cache.
The first generation of this family is introduced with AM642.
See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2
Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Change-Id: I8cd2c1c9a9434646d0c72fca3162dd5bc9bd692a
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