History log of /rk3399_ARM-atf/plat/ti/common/plat_common.mk (Results 1 – 4 of 4)
Revision Date Author Comments
# 80684b7e 13-Oct-2025 Olivier Deprez <olivier.deprez@arm.com>

Merge "fix(cm): deprecate use of NS_TIMER_SWITCH" into integration


# ccf67965 21-Aug-2025 Sumit Garg <sumit.garg@oss.qualcomm.com>

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view availa

fix(cm): deprecate use of NS_TIMER_SWITCH

On AArch64, secure world has it's own EL3 physical timer registers
accessible to secure EL1 in absence of S-EL2. With S-EL2 there is
virtualized view available for EL1 timer registers. So it is
unreasonable for secure world to use non-secure EL1 physical timer
registers. Moreover, the non-secure operating system (Linux in our case)
relies heavily on these EL1 physical timer registers for scheduling
decisions. If NS_TIMER_SWITCH is enabled, it simply breaks the preemption
model of the non-secure world by disabling non-secure timer interrupts
leading to RCU stalls being observed on long running secure world tasks.

The only arch timer register which will benefit from context management
is cntkctl_el1: Counter-timer Kernel Control Register. This enables the
secure and non-secure worlds to independently control accesses to EL0
for counter-timer registers. This is something that OP-TEE uses to
enable ftrace feature for Trusted Applications and SPM_MM uses for EL0
access as well.

Lets enable context management of cntkctl_el1 by default and deprecate
conditional context management of non-secure EL1 physical timer
registers for whom there isn't any upstream user. With that deprecate
this NS_TIMER_SWITCH build option which just adds confusion for the
platform maintainers. It will be eventually dropped following
deprecation policy of TF-A.

Reported-by: Stauffer Thomas MTANA <thomas.stauffer@mt.com>
Reported-by: Andrew Davis <afd@ti.com>
Change-Id: Ifb3a919dc0bf8c05c38895352de5fe94b4f4387e
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

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# 7147732a 09-Apr-2025 Govindraj Raja <govindraj.raja@arm.com>

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): ad

Merge changes from topic "ti-am62l-mailbox-psci-base-support" into integration

* changes:
feat(ti): introduce basic support for the AM62L
feat(ti): introduce PSCI Driver for AM62L
feat(ti): add support for TI mailbox driver
refactor(ti): move out k3/common to ti/common
refactor(ti): introduce ti_bl31_setup
refactor(ti): add the sec hdr to the ti sci msg
refactor(ti): rename the k3_sec_proxy_chan_id
refactor(ti): rename the sec_proxy functions
refactor(ti): add top level ti_sci transport layer
refactor(ti): move TI SCI and sec proxy to drivers

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# bfac44b5 24-Mar-2025 Dhruva Gole <d-gole@ti.com>

refactor(ti): move out k3/common to ti/common

This will allow us to support more platforms that share commonalities
like the k3_gicv3, console, helpers, etc.
With this new common folder location, we

refactor(ti): move out k3/common to ti/common

This will allow us to support more platforms that share commonalities
like the k3_gicv3, console, helpers, etc.
With this new common folder location, we can move the previously
created ti_bl31_setup file into the new location so it can be shared
across multiple TI SoCs when need comes.
With this, also update all copyright dates.

Change-Id: Ie4365e32cd3b4b5870fe2cd03843400506e46265
Signed-off-by: Dhruva Gole <d-gole@ti.com>

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