Merge changes I26cefbb5,I6a8b3528,I323fb741 into integration

* changes:
fix(stm32mp2): set PLAT_MAX_PWR_LVL to one
feat(stm32mp2): boot BL33 at EL1 or EL2
feat(stm32mp2): disable unsupported f

Merge changes I26cefbb5,I6a8b3528,I323fb741 into integration

* changes:
fix(stm32mp2): set PLAT_MAX_PWR_LVL to one
feat(stm32mp2): boot BL33 at EL1 or EL2
feat(stm32mp2): disable unsupported features

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feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_U

feat(stm32mp2): boot BL33 at EL1 or EL2

STM32 MPUs use U-Boot as BL33. It can handle being booted at EL2.
Add a new STM32MP_BL33_EL1 config boolean. If defined BL33 will start
at EL1 and with INIT_UNUSED_NS_EL2 defined to Iiitialize the unused EL2
registers.

Change BL33 spsr parameter in bl2_mem_params_descs[] to use MODE_EL2
or MODE_EL1 depending on this flag. Default to MODE_EL1 as kernel
isn't able to boot at EL2 yet.

Change-Id: I6a8b35280d454d8140d7b28f0a5fc9b9a5093d6d
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>

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Merge changes I8d62253e,I320a0585 into integration

* changes:
feat(stm32mp2): initialize gic and delay timer in bl31_plat_arch_setup
feat(stm32mp2): add BL31 device tree support

feat(stm32mp2): add BL31 device tree support

BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in

feat(stm32mp2): add BL31 device tree support

BL31 will need to access a device tree for several configurations (UART,
GIC, OTP mapping...).
Create a BL31 device tree (SOC_FW_CONFIG). It is loaded in DDR, in a
spare area.

Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I320a05859e1aa3dd8db9a274e7201075a8c250c2

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Merge changes Ic79429c3,Ie2d5272e,Iec73f9c5,Ie63f48dc,I951da75a, ... into integration

* changes:
feat(stm32mp2): load FW binaries to DDR
feat(stm32mp2-fdts): update STM32MP257F-EV1 DT
feat(fdt

Merge changes Ic79429c3,Ie2d5272e,Iec73f9c5,Ie63f48dc,I951da75a, ... into integration

* changes:
feat(stm32mp2): load FW binaries to DDR
feat(stm32mp2-fdts): update STM32MP257F-EV1 DT
feat(fdts): add DDR4 files for STM32MP2
feat(stm32mp25-fdts): add DDRCTRL and DDRPHY settings in DDR node
feat(stm32mp25-fdts): add DDR power supplies
feat(stm32mp2-fdts): add memory node
feat(stm32mp2): enable DDR driver

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feat(stm32mp2): load FW binaries to DDR

Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U

feat(stm32mp2): load FW binaries to DDR

Now that DDR is initialized, we can load the different firmware
parts: BL32 (OP-TEE header), BL32 extra1 (OP-TEE), HW_CONFIG (U-Boot
device tree) and BL33 (U-Boot).

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ic79429c3bd4516c339f91a10e0b3f2828bf6c392

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Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat

Merge changes I09ab0a5c,I87d0a492,I613a52ae,I2fcd8d32,Ie91527a7, ... into integration

* changes:
feat(stm32mp2): manage DDR FW via FIP
feat(stm32mp2): introduce DDR type compilation flags
feat(stm32mp2): add RISAB registers description
feat(stm32mp2-fdts): add BL31 info in fw-config
feat(stm32mp2): add minimal support for BL31
feat(st): manage BL31 FCONF load_info struct

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feat(stm32mp2): manage DDR FW via FIP

This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.

DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the

feat(stm32mp2): manage DDR FW via FIP

This feature is enabled by default using STM32MP_DDR_FIP_IO_STORAGE.

DDR firmware binary is loaded from FIP to SRAM1 which needs to be
mapped.
Only half of the SRAM1 will be allocated to TF-A.
RISAB3 has to be configured to allow access to SRAM1.
Add image ID and update maximum number on platform side also.

Fill related descriptor information, add policy and update numbers.
DDR_TYPE variable is used to identify binary file, and image is now
added in the fiptool command line.

The DDR PHY firmware is not in TF-A repository. It can be found at
https://github.com/STMicroelectronics/stm32-ddr-phy-binary
To ease the selection of the firmware path, STM32MP_DDR_FW_PATH is added
to platform.mk file.

Change-Id: I09ab0a5c63406055a7b5ccd16d65e443de47ca2f
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>

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feat(stm32mp2): add minimal support for BL31

Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other bina

feat(stm32mp2): add minimal support for BL31

Add the required files to compile BL31 on STM32MP2.
Update BL2 configuration to load BL31. The platform boots until BL31,
but stops here as no other binaries are loaded as DDR is not
initialized.
At runtime, BL31 will use only the first half of the SYSRAM, the upper
half will be used for non-secure DMA LLIs. To be sure nothing from this
area is still in the cache, invalidate the upper SYSRAM before enabling
BL31 cache. BL31 should then map only first half of the SYSRAM. But it
must temporarily map the upper half read-only, as this is where we will
retrieve BL2 parameters, used to fill registers for next boot stages.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: Ie91527a7a26625624b4b3c65fb6a0ca9dd355dbd

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Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config fil

Merge changes from topic "stm32mp2_bl2_updates" into integration

* changes:
feat(stm32mp2): load fw-config file
feat(stm32mp2): add fw-config compilation
feat(stm32mp2-fdts): add fw-config files for STM32MP257F-EV1
feat(stm32mp2-fdts): add fw-config file
feat(stm32mp2-fdts): add clock tree for STM32MP257F-EV1
feat(stm32mp2): enable DDR sub-system clock
feat(stm32mp2): add fixed regulators support
feat(stm32mp2): print board info
feat(stm32mp2): display CPU info
feat(stm32mp2): get chip ID
feat(stm32mp2): add BL2 boot first steps
feat(stm32mp2): add defines for the PWR peripheral
feat(stm32mp2-fdts): add SD-card and eMMC support on STM32MP257F-EV1
feat(stm32mp2-fdts): add sdmmc pins definition
feat(stm32mp2-fdts): add sdmmc nodes in SoC DT file
feat(stm32mp2-fdts): add io_policies
feat(stm32mp2-fdts): remove pins-are-numbered

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feat(stm32mp2): load fw-config file

Add FW_CONFIG_ID entry in bl2_mem_params_descs to be loaded, and add
its parsing in bl2_plat_handle_post_image_load().

Signed-off-by: Yann Gautier <yann.gautier@

feat(stm32mp2): load fw-config file

Add FW_CONFIG_ID entry in bl2_mem_params_descs to be loaded, and add
its parsing in bl2_plat_handle_post_image_load().

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I151289474325067204ffae62e17c2e1e00f79b1c

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Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinc

Merge changes from topic "stm32mp2" into integration

* changes:
feat(stm32mp2): generate stm32 file
feat(stm32mp2-fdts): add stm32mp257f-ev1 board
feat(stm32mp2-fdts): introduce stm32mp25 pinctrl files
feat(stm32mp2-fdts): introduce stm32mp25 SoCs family
feat(stm32mp2): add console configuration
feat(st): add RCC registers list
feat(st-uart): add AARCH64 stm32_console driver
feat(st): introduce new platform STM32MP2
feat(dt-bindings): add the STM32MP2 clock and reset bindings
docs(changelog): add scopes for STM32MP2
feat(docs): introduce STM32MP2 doc
refactor(docs): add a sub-menu for ST platforms
refactor(st): move plat_image_load.c
refactor(st): rename PLAT_NB_FIXED_REGS
refactor(st): move some storage definitions to common part
refactor(st): move SDMMC definitions to driver
feat(st-clock): stub fdt_get_rcc_secure_state
feat(st-clock): allow aarch64 compilation of STGEN functions
feat(st): allow AARCH64 compilation for common code
refactor(st): rename QSPI macros

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feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc

feat(st): introduce new platform STM32MP2

This new STMicroelectronics SoC is based on a dual Cortex-A35.
For the moment, only BL2 is compiled with the common parts for ST
platforms.

Change-Id: I1bc4e6835dba4230359ea9b26d736791e27258aa
Signed-off-by: Yann Gautier <yann.gautier@st.com>

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