feat(rk3588): report actual measured PVTPLL clocks

The GRF block includes a counter that measures PVTPLL clock pulses after
the CON1 register, exposed via STATUS1 and STATUS2. The counter uses an
in

feat(rk3588): report actual measured PVTPLL clocks

The GRF block includes a counter that measures PVTPLL clock pulses after
the CON1 register, exposed via STATUS1 and STATUS2. The counter uses an
input clock that can be configured in the CRU block; however, in the
current ATF implementation it is always XIN = 24 MHz.

The counter accumulates PVTPLL pulses for a window of:

measurement_time = CON1 / input_frequency

Since CON1 is fixed to 24, the current implementation measures over:

24 / 24 MHz = 1 µs

The resulting count is stored in the lower 14 bits of STATUS2.

This commit waits 2 µs (ensuring the 1 µs accumulation period completes)
and computes the PVTPLL frequency from the measured value. While CON1
could be increased for higher accuracy (as long as the 14-bit counter
does not overflow), this change keeps the existing 1 µs window for
simplicity.

With this feature, PVTPLL frequency can be measured with ~1 MHz
accuracy, instead of reporting only the configured frequency, which can
hide information related to chip degradation and environmental effects
impacting PVTPLL clocks.

Ideally the flow of measuring PVTPLL clocks should be the same for the
rest of RK35xx devices with minor tweaks at most.

Change-Id: Idc18246e8d794777f0dacc7820f15fcecc00af33
Signed-off-by: Hüseyin BIYIK <boogiepop@gmx.com>

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feat(rk3588): support SCMI for clock/reset domain

rockchip scmi clock controls clocks which only available in secure mode.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I5

feat(rk3588): support SCMI for clock/reset domain

rockchip scmi clock controls clocks which only available in secure mode.

Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I5b983877a5b4e8acababbf7e0a3e2725e6479e08

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