| #
1c63cd61 |
| 06-Nov-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "qti-rb3gen2" into integration
* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio
Merge changes from topic "qti-rb3gen2" into integration
* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot
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| #
c48d0aef |
| 25-Sep-2025 |
Sumit Garg <sumit.garg@oss.qualcomm.com> |
feat(qti): add TF-A BL2 common platform framework
Currently QTI pltforms only supports coreboot as the second stage
bootloader. Lets enable support for TF-A BL2 as the common reference
second stage
feat(qti): add TF-A BL2 common platform framework
Currently QTI pltforms only supports coreboot as the second stage
bootloader. Lets enable support for TF-A BL2 as the common reference
second stage bootloader which is able to support a variety of normal
world OS bootloaders (BL33) like edk2, U-Boot, coreboot-depthcharge etc.
The common reference boot flow should look like following on QTI
platforms:
PBL (ROM) -> XBL -> BL2 -> BL31 -> BL33 -> Normal world OS
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--> BL32
As of now XBL is performing DRAM initialization and loads two set of
images for BL2 and FIP into DRAM from flash after performing secure boot
checks if enabled. Then BL2 does the FIP parsing from DRAM and loads
payloads at appropriate addresses as per the FIP configuration.
Note here that BL2 image is loaded from TZ partition on UFS flash which
by default requires QTI secure boot checks.
Change-Id: Ice73905bff39291fa417389cb84dabe455c3f0ba
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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| #
54b3fc63 |
| 04-Nov-2022 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(qti): updated soc version for sc7180 and sc7280" into integration
|
| #
39fdd3d8 |
| 01-Nov-2022 |
Bharath N <quic_bharn@quicinc.com> |
feat(qti): updated soc version for sc7180 and sc7280
SMCCC_GET_SOC_VERSION SMC will return soc id to distinguish
different varaints in sc7180 and sc7280
Signed-off-by: Bharath N <quic_bharn@quicinc
feat(qti): updated soc version for sc7180 and sc7280
SMCCC_GET_SOC_VERSION SMC will return soc id to distinguish
different varaints in sc7180 and sc7280
Signed-off-by: Bharath N <quic_bharn@quicinc.com>
Change-Id: I72ea4bdb8193c816ba249c1e0755784c9b9bb7da
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| #
17e76b5e |
| 02-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(plat/qti): fix to support cpu errata" into integration
|
| #
6cc743cf |
| 04-Apr-2022 |
Saurabh Gorecha <quic_sgorecha@quicinc.com> |
feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf1416
feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e
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| #
a4c979ad |
| 26-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
* changes:
qti/sc7180: Do shutdown handling outside qtiseclib
qti: Add SPMI PMIC arbitrator driver
qti/sc7180: Fix GIC-600 support
Merge changes I6bf1db15,I8631c34a,Id76ada14 into integration
* changes:
qti/sc7180: Do shutdown handling outside qtiseclib
qti: Add SPMI PMIC arbitrator driver
qti/sc7180: Fix GIC-600 support setting
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| #
522a2277 |
| 21-Feb-2019 |
Julius Werner <jwerner@chromium.org> |
qti/sc7180: Do shutdown handling outside qtiseclib
With an open source SPMI driver we can now remove qtiseclib involvement
in reset and shutdown handling by setting the required registers
directly.
qti/sc7180: Do shutdown handling outside qtiseclib
With an open source SPMI driver we can now remove qtiseclib involvement
in reset and shutdown handling by setting the required registers
directly.
Change-Id: I6bf1db15734048df583daa2a4ee98701c6ece621
Signed-off-by: Julius Werner <jwerner@chromium.org>
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| #
37a12f04 |
| 10-Aug-2020 |
Julius Werner <jwerner@chromium.org> |
Merge "sc7180 platform support" into integration
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| #
5bd9c17d |
| 22-Apr-2020 |
Saurabh Gorecha <sgorecha@codeaurora.org> |
sc7180 platform support
Adding support for QTI CHIP SC7180 on ATF
Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Mauli
sc7180 platform support
Adding support for QTI CHIP SC7180 on ATF
Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
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