SPMD: [tegra] rename el1_sys_regs structure to sys_regs

Renamed the structure according to a SPMD refactoring
introduced in <c585d07aa> since this structure is used
to service both EL1 and EL2 as op

SPMD: [tegra] rename el1_sys_regs structure to sys_regs

Renamed the structure according to a SPMD refactoring
introduced in <c585d07aa> since this structure is used
to service both EL1 and EL2 as opposed to serving only EL1.

Change-Id: I23b7c089e53f617157a4b4e6443acce50d85c3b5
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

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spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data struct

spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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LS 16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data s

LS 16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: Ifd6aff1064ba1c3c029cdd8a83f715f7a9976db5
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data stru

16550: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I5c2fe3b6a667acf80c808cfec4a64059a2c9c25f
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Tegra: spe: uninit console on a timeout

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmwar

Tegra: spe: uninit console on a timeout

There are chances a denial-of-service attack, if an attacker
removes the SPE firmware from the system. The console driver
would end up waiting for the firmware to respond indefinitely.
The console driver must detect such scenarios and uninit the
interface as a result.

This patch adds a timeout to the interaction with the SPE
firmware and uninits the interface if it times out.

Change-Id: I06f27a858baed25711d41105b4110865f1a01727
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the

Tegra: handler to check support for System Suspend

Tegra210 SoCs need the sc7entry-fw to enter System Suspend mode,
but there might be certain boards that do not have this firmware
blob. To stop the NS world from issuing System suspend entry
commands on such devices, we ned to disable System Suspend from
the PSCI "features".

This patch removes the System suspend handler from the Tegra PSCI
ops, so that the framework will disable support for "System Suspend"
from the PSCI "features".

Original change by: kalyani chidambaram <kalyanic@nvidia.com>

Change-Id: Ie029f82f55990a8b3a6debb73e95e0e218bfd1f5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp_ipc: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

Tegra: bpmp_ipc: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'ipc_send_req_atomic'
handler to reduce the McCabe Cyclomatic Complexity for this function

Change-Id: I20fef79a771301e1c824aea72a45ff83f97591d5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: platform handler to relocate BL32 image

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZD

Tegra: platform handler to relocate BL32 image

This patch provides platforms an opportunity to relocate the
BL32 image, during cold boot. Tegra186 platforms, for example,
relocate BL32 images to TZDRAM memory as the previous bootloader
relies on BL31 to do so.

Change-Id: Ibb864901e43aca5bf55d8c79e918b598c12e8a28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: common: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

co

Tegra: common: improve cyclomatic complexity

Code complexity is a good indication of maintainability versus
testability of a piece of software.

ISO26262 introduces the following thresholds:

complexity < 10 is accepted
10 <= complexity < 20 has to be justified
complexity >= 20 cannot be accepted

Rationale is that number of test cases to fully test a piece of
software can (depending on the coverage metrics) grow exponentially
with the number of branches in the software.

This patch removes redundant conditionals from 'bl31_early_platform_setup'
handler to reduce the McCabe Cyclomatic Complexity for this function.

Change-Id: Ifb628e33269b388f9323639cd97db761a7e049c4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: secure PMC hardware block

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and Sys

Tegra210: secure PMC hardware block

This patch sets the "secure" bit to mark the PMC hardware block
as accessible only from the secure world. This setting must be
programmed during cold boot and System Resume.

The sc7entry-fw, running on the COP, needs access to the PMC block
to enter System Suspend state, so "unlock" the PMC block before
passing control to the COP.

Change-Id: I00e39a49ae6b9f8c8eafe0cf7ff63fe6a67fdccf
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

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Tegra: delay_timer: support for physical secure timer

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure tim

Tegra: delay_timer: support for physical secure timer

This patch modifies the delay timer driver to switch to the ARM
secure physical timer instead of using Tegra's on-chip uS timer.

The secure timer is not accessible to the NS world and so eliminates
an important attack vector, where the Tegra timer source gets switched
off from the NS world leading to a DoS attack for the trusted world.

This timer is shared with the S-EL1 layer for now, but later patches
will mark it as exclusive to the EL3 exception mode.

Change-Id: I2c00f8cb4c48b25578971c626c314603906ad7cc
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: memctrl: lock mc stream id security config

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the fol

Tegra194: memctrl: lock mc stream id security config

This patch locks most of the stream id security config registers as
per HW guidance.

This patch keeps the stream id configs unlocked for the following
clients, to allow some platforms to still function, until they make
the transition to the latest guidance.

- ISPRA
- ISPFALR
- ISPFALW
- ISPWA
- ISPWA1
- ISPWB
- XUSB_DEVR
- XUSB_DEVW
- XUSB_HOSTR
- XUSB_HOSTW
- VIW
- VIFALR
- VIFALW

Change-Id: I66192b228a0a237035938f498babc0325764d5df
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra210: resume PMC hardware block for all platforms

The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause pro

Tegra210: resume PMC hardware block for all platforms

The PMC hardware block resume handler was called for Tegra210
platforms, only if the sc7entry-fw was present on the device.
This would cause problems for devices that do not support this
firmware.

This patch fixes this logic and resumes the PMC block even if
the sc7entry-fw is not present on the device.

Change-Id: I6f0eb7878126f624ea98392f583ed45a231d27db
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>

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Tegra: macro for legacy WDT FIQ handling

This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this suppor

Tegra: macro for legacy WDT FIQ handling

This patch adds the macro to enable legacy FIQ handling to the common
Tegra makefile. The default value of this macro is '0'. Platforms that
need this support should enable it from their makefiles.

This patch also helps fix violation of Rule 20.9.

Rule 20.9 "All identifiers used in the controlling expression of #if
of #elif preprocessing directives shall be #define'd before
evaluation"

Change-Id: I4f0c9917c044b5b1967fb5e79542cd3bf6e91f18
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c96

Tegra186: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra186 platforms.

Change-Id: Ifceb304bfbd805f415bb6205c9679602ecb47b53
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra210: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2f

Tegra210: enable higher performance non-cacheable load forwarding

This patch enables higher performance non-cacheable load forwarding for
Tegra210 platforms.

Change-Id: I11d0ffc09aca97d37386f283f2fbd2483d51fd28
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: declare nvg_roc_clean_cache_trbits()

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

C

Tegra194: mce: declare nvg_roc_clean_cache_trbits()

This patch adds the nvg_roc_clean_cache_trbits() function prototype
to mce_private.h to fix compilation failures seen with the Tegra194
builds.

Change-Id: I313556f6799792fc0141afb5822cc157db80bc47
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra186: memctrl: lock stream id security config

Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-b

Tegra186: memctrl: lock stream id security config

Tegra186 is in production so lock stream id security configs
for all the clients.

Change-Id: I64bdd5a9f12319a543291bfdbbfc1559d7a44113
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

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Tegra194: remove support for simulated system suspend

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now

Tegra194: remove support for simulated system suspend

This patch removes support for simulated system suspend for Tegra194
platforms as we have actual silicon platforms that support this
feature now.

Change-Id: I9ed1b002886fed7bbc3d890a82d6cad67e900bae
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: mce: fix multiple MISRA issues

This patch fixes violations of the following MISRA rules

* Rule 8.5 "An external object or function shall be declared once in
one and only one

Tegra194: mce: fix multiple MISRA issues

This patch fixes violations of the following MISRA rules

* Rule 8.5 "An external object or function shall be declared once in
one and only one file"
* Rule 10.3 "The value of an expression shall not be assigned to an
object with a narrower essential type or of a different
esential type category"

Change-Id: I4314cd4fea0a4adc6665868dd31e619b4f367e14
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: bpmp: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 5.7 "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inapp

Tegra: bpmp: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 5.7 "A tag name shall be a unique identifier"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.3 "The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category"
* Rule 10.4 "Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category"
* Rule 20.7 "Expressions resulting from the expansion of macro parameters
shall be enclosed in parentheses"
* Rule 21.1 "#define and #undef shall not be used on a reserved identifier
or reserved macro name"

Change-Id: I83cbe659c2d72e76dd4759959870b57c58adafdf
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra194: se: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 8.4 "A compatible declaration shall be visible when an object or
function with

Tegra194: se: fix multiple MISRA issues

This patch fixes violations for the following MISRA rules

* Rule 8.4 "A compatible declaration shall be visible when an object or
function with external linkage is defined"
* Rule 10.1 "Operands shall not be of an inappropriate essential type"
* Rule 10.6 "Both operands of an operator in which the usual arithmetic
conversions are perdormed shall have the same essential type
category"
* Rule 17.7 "The value returned by a function having non-void return
type shall be used"

Change-Id: I171ac8340de729fd7be928fa0c0694e9bb8569f0
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: compile PMC driver for Tegra132/Tegra210 platforms

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platfo

Tegra: compile PMC driver for Tegra132/Tegra210 platforms

The PMC driver is used only by Tegra210 and Tegra132 platforms. This
patch removes pmc.c from the common makefile and moves it to the
platform specific makefiles.

As a result, the PMC code from common code has been moved to Tegra132
and Tegra210 platform ports.

Change-Id: Ia157f70e776b3eff3c12eb8f0f02d30102670a98
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler

This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Chang

Tegra: memctrl_v2: remove weakly defined TZDRAM setup handler

This patch removes the per-platform, weakly defined TZDRAM setup handler,
as all affected platforms implement the actual handler.

Change-Id: I95d04b2a771bc5d673e56b097d45c493fa388ee8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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Tegra: remove weakly defined per-platform SiP handler

This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition

Tegra: remove weakly defined per-platform SiP handler

This patch removes the weakly defined per-platform SiP handler
as all platforms implement this handler, defeating the need for
a weak definition.

Change-Id: Id4c7e69163d2635de1813f5a385ac874253a8da9
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

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