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56887791 |
| 12-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "tegra-downstream-03102020" into integration
* changes: Tegra210: Remove "unsupported func ID" error msg Tegra210: support for secure physical timer spd: tlkd: secure
Merge changes from topic "tegra-downstream-03102020" into integration
* changes: Tegra210: Remove "unsupported func ID" error msg Tegra210: support for secure physical timer spd: tlkd: secure timer interrupt handler Tegra: smmu: export handlers to read/write SMMU registers Tegra: smmu: remove context save sequence Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194 Tegra194: memctrl: lock some more MC SID security configs Tegra194: add SE support to generate SHA256 of TZRAM Tegra194: store TZDRAM base/size to scratch registers Tegra194: fix warnings for extra parentheses
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| #
a391d494 |
| 03-Aug-2018 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra: smmu: remove context save sequence
SMMU and MC registers are saved as part of the System Suspend sequence. The register list includes some NS world SMMU registers that need to be saved by NS
Tegra: smmu: remove context save sequence
SMMU and MC registers are saved as part of the System Suspend sequence. The register list includes some NS world SMMU registers that need to be saved by NS world software instead. All that remains as a result are the MC registers.
This patch moves code to MC file as a result and renames all the variables and defines to use the MC prefix instead of SMMU. The Tegra186 and Tegra194 platform ports are updated to provide the MC context register list to the parent driver. The memory required for context save is reduced due to removal of the SMMU registers.
Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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| #
30490b15 |
| 06-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19
Tf2.0 tegra downstream rebase 1.25.19
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28f45bb8 |
| 26-Oct-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra186: smmu: add support for backup multiple smmu regs
Modifying smmu macros to pass base address of smmu so that it can be used with multiple smmus.
Added macro for combining smmu backup regs t
Tegra186: smmu: add support for backup multiple smmu regs
Modifying smmu macros to pass base address of smmu so that it can be used with multiple smmus.
Added macro for combining smmu backup regs that can be used for multiple smmus.
Change-Id: I4f3bb83d66d5df14a3b91bc82f7fc26ec8e4592e Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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bc5e79cd |
| 25-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1776 from vwadekar/tf2.0-tegra-downstream-rebase-1.22.19
Tf2.0 tegra downstream rebase 1.22.19
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| #
ab2eb455 |
| 04-Aug-2017 |
Puneet Saxena <puneets@nvidia.com> |
Tegra: memctrl_v2: platform handlers to program MSS
Introduce platform handlers to program the MSS settings. This allows the current driver to scale to future chips.
Change-Id: I40a27648a1a3c73b1ce
Tegra: memctrl_v2: platform handlers to program MSS
Introduce platform handlers to program the MSS settings. This allows the current driver to scale to future chips.
Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
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c40c88f8 |
| 21-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1764 from vwadekar/tf2.0-tegra-downstream-rebase-1.7.19
Tf2.0 tegra downstream rebase 1.7.19
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bc5a86f7 |
| 25-Jul-2017 |
Steven Kao <skao@nvidia.com> |
Tegra: smmu: add a hook to get number of devices
This patch adds a hook to get the number of smmu devices and removes the NUM_SMMU_DEVICES macro.
Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc4
Tegra: smmu: add a hook to get number of devices
This patch adds a hook to get the number of smmu devices and removes the NUM_SMMU_DEVICES macro.
Change-Id: Ia8dba7e9304224976b5da688b9e4b5438f11cc41 Signed-off-by: Steven Kao <skao@nvidia.com>
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9e7a2436 |
| 28-Jun-2017 |
Anthony Zhou <anzhou@nvidia.com> |
Tegra186: fix defects flagged by MISRA scan
Main fixes:
Remove unused type conversion
Fix invalid use of function pointer [Rule 1.3]
Fix variable essential type doesn't match [Rule 10.3]
Voided
Tegra186: fix defects flagged by MISRA scan
Main fixes:
Remove unused type conversion
Fix invalid use of function pointer [Rule 1.3]
Fix variable essential type doesn't match [Rule 10.3]
Voided non c-library functions whose return types are not used [Rule 17.7]
Change-Id: I23994c9d4d6a240080933d848d2b03865acaa833 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
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| #
9a207532 |
| 04-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1726 from antonio-nino-diaz-arm/an/includes
Sanitise includes across codebase
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09d40e0e |
| 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - inclu
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them).
For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems.
Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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36332806 |
| 21-Mar-2018 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #1304 from antonio-nino-diaz-arm/an/fix-copyright
tegra: Use SPDX license identifier
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41376c3a |
| 08-Mar-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
tegra: Use SPDX license identifier
Change-Id: I770b2db68c8d115d10067bb557e32b5e269c94a5 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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0f22bef3 |
| 29-Apr-2017 |
Scott Branden <sbranden@users.noreply.github.com> |
Merge branch 'integration' into tf_issue_461
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3d21c945 |
| 16-Apr-2017 |
davidcunado-arm <david.cunado@arm.com> |
Merge pull request #899 from vwadekar/tegra186-platform-support-v6
Tegra186 platform support v6
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986e333d |
| 02-Jan-2017 |
Pritesh Raithatha <praithatha@nvidia.com> |
Tegra: smmu: platform handler for SMMU settings
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend.
Original-change-by: Prite
Tegra: smmu: platform handler for SMMU settings
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend.
Original-change-by: Pritesh Raithatha <praithatha@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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