| 7afd4637 | 19-Jan-2016 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra186: support for C6/C7 CPU_SUSPEND states
This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
an idle state while C7 is a powerdown state.
The MCE block takes care of the entry
Tegra186: support for C6/C7 CPU_SUSPEND states
This patch adds support for the C6 and C7 CPU_SUSPEND states. C6 is
an idle state while C7 is a powerdown state.
The MCE block takes care of the entry/exit to/from these core power
states and hence we call the corresponding MCE handler to process
these requests. The NS driver passes the tentative time that the
core is expected to stay in this state as part of the power_state
parameter, which we store in a per-cpu array and pass it to the
MCE block.
Change-Id: I152acb11ab93d91fb866da2129b1795843dfa39b
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| d48c0c45 | 30-Dec-2015 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra: memctrl_v2: secure the on-chip TZSRAM memory
This patch programs the Memory controller's control registers
to disable non-secure accesses to the TZRAM. In case these
registers are already pro
Tegra: memctrl_v2: secure the on-chip TZSRAM memory
This patch programs the Memory controller's control registers
to disable non-secure accesses to the TZRAM. In case these
registers are already programmed by the BL2/BL30, then the
driver just bails out.
Change-Id: Ia1416988050e3d067296373060c717a260499122
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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