Merge changes from topic "console_t_cleanup" into integration

* changes:
marvell: Consolidate console register calls
uniphier: Use generic console_t data structure
spe: Use generic console_t d

Merge changes from topic "console_t_cleanup" into integration

* changes:
marvell: Consolidate console register calls
uniphier: Use generic console_t data structure
spe: Use generic console_t data structure
LS 16550: Use generic console_t data structure
stm32: Use generic console_t data structure
rcar: Use generic console_t data structure
a3700: Use generic console_t data structure
16550: Use generic console_t data structure
imx: Use generic console_t data structure

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spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data struct

spe: Use generic console_t data structure

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: I75dbfafb67849833b3f7b5047e237651e3f553cd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: int

Merge changes from topic "tegra-downstream-092319" into integration

* changes:
Tegra194: add support to reset GPU
Tegra194: memctrl: fix logic to check TZDRAM config register access
Tegra: introduce plat_enable_console()
Tegra: include: drivers: introduce spe.h
Tegra194: update nvg header to v6.4
Tegra194: mce: enable strict checking
Tegra194: CC6 state from last offline CPU in the cluster
Tegra194: console driver compilation from platform makefiles
Tegra194: memctrl: platform handler for TZDRAM setup
Tegra194: memctrl: override SE client as coherent
Tegra194: save system suspend entry marker to TZDRAM
Tegra194: helper functions for CPU rst handler and SMMU ctx offset
Tegra194: cleanup references to Tegra186
Tegra194: mce: display NVG header version during boot
Tegra194: mce: fix cg_cstate encoding format
Tegra194: drivers: SE and RNG1/PKA1 context save support
Tegra194: rename secure scratch register macros
Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
Tegra194: mce: remove unsupported functionality
Tegra194: sanity check target cluster during core power on
Tegra194: fix defects flagged by MISRA scan
Tegra194: mce: fix defects flagged by MISRA scan
Tegra194: remove the GPU reset register macro
Tegra194: MC registers to allow CPU accesses to TZRAM
Tegra194: increase MAX_MMAP_REGIONS macro value
Tegra194: update nvg header to v6.1
Tegra194: update cache operations supported by the ROC
Tegra194: memctrl: platform handlers to reprogram MSS
Tegra194: core and cluster count values
Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
Tegra194: add MC_SECURITY mask defines
Tegra194: Update wake mask, wake time for cpu offlining
Tegra194: program stream ids for XUSB
Tegra194: Update checks for c-state stats
Tegra194: smmu: fix mask for board revision id
Tegra194: smmu: ISO support
Tegra194: Initialize smmu on system suspend exit
Tegra194: Update cpu core-id calculation
Tegra194: read-modify-write ACTLR_ELx registers
Tegra194: Enable fake system suspend
Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
Tegra194: platform support for memctrl/smmu drivers
Tegra194: Support for cpu suspend

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Tegra: include: drivers: introduce spe.h

This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.

S

Tegra: include: drivers: introduce spe.h

This patch introduces a header file for the spe-console driver. This
file currently provides a device struct and a registration function
call for clients.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799

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