| #
02309a84 |
| 27-May-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes Ia29fd72f,I31b359ce,I1296aaff,I30e1ee7f,Ib4a3593e, ... into integration
* changes:
feat(mt8196): add SMMU SID stub implementation
feat(mt8196): add SLBC SiP handler
feat(mt8196):
Merge changes Ia29fd72f,I31b359ce,I1296aaff,I30e1ee7f,Ib4a3593e, ... into integration
* changes:
feat(mt8196): add SMMU SID stub implementation
feat(mt8196): add SLBC SiP handler
feat(mt8196): add CPU QoS stub implementation
refactor(mediatek): update EMI stub implementation
feat(mediatek): add APIs exposed to the static library
feat(mt8196): add MMinfra support
feat(mt8196): add UFS functions used by the static library
show more ...
|
| #
00105882 |
| 28-Apr-2025 |
Yidi Lin <yidilin@chromium.org> |
refactor(mediatek): update EMI stub implementation
Refactor EMI stub implementation with following changes.
- Move the SiP call handlers to TF-A upstream.
- Move EMI definition used by APUSYS to pla
refactor(mediatek): update EMI stub implementation
Refactor EMI stub implementation with following changes.
- Move the SiP call handlers to TF-A upstream.
- Move EMI definition used by APUSYS to platform_def.h.
- Remove CONFIG_MTK_APUSYS_EMI_SUPPORT.
Change-Id: I30e1ee7f2ea2d6dc3415adba91cbe310af9b5eeb
Signed-off-by: Yidi Lin <yidilin@chromium.org>
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|
| #
999503d2 |
| 24-Dec-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes Ic746571b,I1926cab9,Id70162e9,I3a9b014e,Ic99adba1, ... into integration
* changes:
feat(mt8196): enable APU on mt8196
feat(mt8196): add APU SMMU hardware semaphore operations
fea
Merge changes Ic746571b,I1926cab9,Id70162e9,I3a9b014e,Ic99adba1, ... into integration
* changes:
feat(mt8196): enable APU on mt8196
feat(mt8196): add APU SMMU hardware semaphore operations
feat(mt8196): add smpu protection for APU secure memory
feat(mt8196): add APU RCX DevAPC setting
feat(mt8196): add APU kernel control operations
feat(mt8196): add APU power on/off functions
feat(mt8196): add APUMMU setting
feat(mt8196): enable apusys mailbox mpu protection
feat(mt8196): enable apusys security control
feat(mt8196): add APUSYS AO DevAPC setting
feat(mt8196): add APU power-on init flow
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|
| #
2d134d28 |
| 14-Nov-2024 |
Karl Li <karl.li@mediatek.com> |
feat(mt8196): add APU SMMU hardware semaphore operations
Add APU SMMU hardware semaphore operations to make APU SMMU
able to sync the power status.
Change-Id: I1926cab990fba54a2ea694ac6d9e87135dfb1
feat(mt8196): add APU SMMU hardware semaphore operations
Add APU SMMU hardware semaphore operations to make APU SMMU
able to sync the power status.
Change-Id: I1926cab990fba54a2ea694ac6d9e87135dfb19cf
Signed-off-by: Karl Li <karl.li@mediatek.com>
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|
| #
5e5c57d5 |
| 14-Nov-2024 |
Karl Li <karl.li@mediatek.com> |
feat(mt8196): add APU kernel control operations
Add APU kernel control operations to provide the bootup init functions.
1. Add software workaround for certain operations on mt8196.
2. Add APU logge
feat(mt8196): add APU kernel control operations
Add APU kernel control operations to provide the bootup init functions.
1. Add software workaround for certain operations on mt8196.
2. Add APU logger operations.
3. Add function to clear mbox spare register, which is used in APU
booting process.
4. Add function to setup CE binary to make sure the CE binary version
is align with the APU firmware.
Change-Id: Ic99adba1409c020c72179ea135e0d4291fc3f384
Signed-off-by: Karl Li <karl.li@mediatek.com>
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| #
e534d4f6 |
| 15-Nov-2024 |
Karl Li <karl.li@mediatek.com> |
feat(mt8196): add APUMMU setting
APUMMU is the MMU in APU, which is responsible for inner address
mapping. The APU kernel driver will setup the APUMMU by SMC call.
Change-Id: Iad7532883e42c288aeb0d
feat(mt8196): add APUMMU setting
APUMMU is the MMU in APU, which is responsible for inner address
mapping. The APU kernel driver will setup the APUMMU by SMC call.
Change-Id: Iad7532883e42c288aeb0d23ab419f4dc6d8630f2
Signed-off-by: Karl Li <karl.li@mediatek.com>
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| #
9059a375 |
| 14-Nov-2024 |
Karl Li <karl.li@mediatek.com> |
feat(mt8196): enable apusys security control
Remap the request from domain 5, 7, 14 to domain 6 and setup security
sideband
Change-Id: I06d377f4bcc542bf22e0a04ffb45cf52b7528a75
Signed-off-by: Karl
feat(mt8196): enable apusys security control
Remap the request from domain 5, 7, 14 to domain 6 and setup security
sideband
Change-Id: I06d377f4bcc542bf22e0a04ffb45cf52b7528a75
Signed-off-by: Karl Li <karl.li@mediatek.com>
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| #
4c8e1f9a |
| 06-Jun-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration
* changes:
feat(mediatek): add APU watchdog timeout control
feat(mt8188): add emi mpu protection for APU sec
Merge changes I21d65a88,I949cfce9,If4249f22,Id0451bd1,I9e930070, ... into integration
* changes:
feat(mediatek): add APU watchdog timeout control
feat(mt8188): add emi mpu protection for APU secure memory
feat(mt8188): add devapc setting of apusys rcx
feat(mt8188): add backup/restore function when power on/off
feat(mediatek): add APU bootup control smc call
feat(mt8188): enable apusys mailbox mpu protect
feat(mt8188): enable apusys domain remap
feat(mt8188): add apusys ao devapc setting
feat(mt8188): increase TZRAM_SIZE from 192KB to 256KB
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| #
ad7673ad |
| 27-Apr-2023 |
Karl Li <karl.li@mediatek.corp-partner.google.com> |
feat(mt8188): enable apusys mailbox mpu protect
Enable apusys mailbox mpu protect.
Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by:
feat(mt8188): enable apusys mailbox mpu protect
Enable apusys mailbox mpu protect.
Change-Id: Idbf67084037b7ecf4926f57a901075f98540ee57
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
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| #
777e3b71 |
| 21-Apr-2023 |
Karl Li <karl.li@mediatek.corp-partner.google.com> |
feat(mt8188): add apusys ao devapc setting
Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set a
feat(mt8188): add apusys ao devapc setting
Apusys ao devapc is a set of control registers inside APU, and it
controls the access permission of APU ao domain.
Moreover, apusys ao devapc must be set after apusys power init, so
we need to place the drivers in TF-A instead of coreboot.
Change-Id: Ife849c32d4dd9dca15432d4b8a51753fde61b148
Signed-off-by: Karl Li <karl.li@mediatek.com>
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
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|
| #
a251f99a |
| 29-Mar-2023 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(mediatek): add APU init flow" into integration
|
| #
52430916 |
| 15-Mar-2023 |
Chungying Lu <chungying.lu@mediatek.corp-partner.google.com> |
feat(mediatek): add APU init flow
The patch brings preparation steps before powering on APU
(AI processing unit)
Change-Id: Ica01e035153ec6f3af0de6ba2c66b17a064f8c89
Signed-off-by: Chungying Lu <ch
feat(mediatek): add APU init flow
The patch brings preparation steps before powering on APU
(AI processing unit)
Change-Id: Ica01e035153ec6f3af0de6ba2c66b17a064f8c89
Signed-off-by: Chungying Lu <chungying.lu@mediatek.com>
show more ...
|