| #
eeb77da6 |
| 06-Oct-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
Merge changes I959d1343,I6992df1a,I687e35cb,Ia5f2ee31,Ifd0bc6aa, ... into integration
* changes:
docs: marvell: update mv_ddr branch
plat: marvell: armada: a3k: rename the UART images archive
plat: marvell: armada: a3k: allow image load to RAM address 0
marvell: comphy: cp110: add support for USB comphy polarity invert
marvell: comphy: cp110: add support for SATA comphy polarity invert
marvell: comphy: cp110: implement erratum IPCE_COMPHY-1353
drivers: marvell: mochi: Update AP incoming masters secure level
plat: marvell: armada: add ccu window for workaround errata-id 3033912
plat: marvell: ap806: implement workaround for errata-id FE-4265711
show more ...
|
| #
ff9cfdc0 |
| 21-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: comphy: cp110: add support for USB comphy polarity invert
The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't re
marvell: comphy: cp110: add support for USB comphy polarity invert
The polarity inversion for USB was not tested due to lack of hw design
which requires it. Currently all supported boards doesn't require USB
phy polarity inversion, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards. Enable the option for the ones that need it.
Change-Id: Ia5f2ee313a93962e94963e2dd8a759ef6d9da369
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| #
38f6daca |
| 21-Jan-2020 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: comphy: cp110: add support for SATA comphy polarity invert
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doe
marvell: comphy: cp110: add support for SATA comphy polarity invert
The cp110 comphy has ability to invert RX and/or TX polarity. Polarity
depends on board design. Currently all supported boards doesn't require
SATA phy polarity invert, therefore COMPHY_POLARITY_NO_INVERT is set for
all boards.
Change-Id: Ifd0bc6aaf8a76a0928132b197422f3193cf020d5
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|
| #
8f09da46 |
| 10-Aug-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: updat
Merge changes from topic "release/14.0" into integration
* changes:
docs: marvell: update PHY porting layer description
docs: marvell: update path in marvell documentation
docs: marvell: update build instructions with CN913x
plat: marvell: octeontx: add support for t9130
plat: marvell: t9130: add SVC support
plat: marvell: t9130: update AVS settings
plat: marvell: t9130: pass actual CP count for load_image
plat: marvell: armada: a7k: add support to SVC validation mode
plat: marvell: armada: add support for twin-die combined memory device
show more ...
|
| #
2c9d2636 |
| 09-Dec-2018 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
plat: marvell: octeontx: add support for t9130
CN-9130 has single CP0 inside the package and 2 additional one from MoChi
interface. In case of db-9130-modular board the MCI interface is routed to:
-
plat: marvell: octeontx: add support for t9130
CN-9130 has single CP0 inside the package and 2 additional one from MoChi
interface. In case of db-9130-modular board the MCI interface is routed to:
- on-board CP115 (MCI0)
- extension board CP115 (MCI1)
The board is based on DIMM DDR.
The 9130 has up to 3CP, and decoding windows looks like below:
(free for further use)
.----------. 0xf800 0000
| CP2 CFG |
'----------' 0xf600 0000
| CP1 CFG |
'----------' 0xf400 0000
| CP0 CFG |
'----------' 0xf200 0000
| AP CFG |
'----------' 0xf000 0000
(free for further use)
.----------. 0xec00 0000
| SPI |
| MEM_MAP | (Currently not opened)
'----------' 0xe800 0000
| PEX2_CP2 |
'----------' 0xe700 0000
| PEX1_CP2 |
'----------' 0xe600 0000
| PEX0-CP2 |
'----------'
.----------. 0xe500 0000
| PEX2_CP1 |
'----------' 0xe400 0000
| PEX1_CP1 |
'----------' 0xe300 0000
| PEX0-CP1 |
'----------'
.----------. 0xe200 0000
| PEX2-CP0 |
'----------' 0xe100 0000
| PEX1-CP0 |
'----------' 0xe000 0000
| PEX0-CP0 |
| 512MB |
'----------' 0xc000 0000
Change-Id: Ia8eee4f96c1043753f74f9da437b9f72ce2d6eb0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
show more ...
|