| #
3a0b28cb |
| 31-Aug-2022 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "chore: use tabs for indentation" into integration
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| #
e2fe267d |
| 29-Aug-2022 |
Jorge Troncoso <jatron@google.com> |
chore: use tabs for indentation
This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding
chore: use tabs for indentation
This patch changes definitions of bl2_mem_params_descs to follow the
TF-A coding style documented at
https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-style.html
Signed-off-by: Jorge Troncoso <jatron@google.com>
Change-Id: I7bd99a50a79499aca0d349e49a3e095e6c5d2f08
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| #
8877af53 |
| 10-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration
* changes:
plat: marvell: armada: mcbin: squash several IO windows into one
plat: marvell: armada: fix BL32
Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration
* changes:
plat: marvell: armada: mcbin: squash several IO windows into one
plat: marvell: armada: fix BL32 extra parameters usage
drivers: marvell: Fix the LLC SRAM driver
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW
plat: marvell: armada: move mg conf related code to appropriate driver
marvell: comphy: start AP FW when comphy AP mode selected
drivers: marvell: mg_conf_cm3: add basic driver
tools: doimage: change the binary image alignment to 16
tools: doimage: migrate to mbedtls v2.8 APIs
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| #
41e8c6fc |
| 13-Nov-2019 |
Marcin Wojtas <mw@semihalf.com> |
plat: marvell: armada: fix BL32 extra parameters usage
Update missing code releated to the BL32 payload.
Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semiha
plat: marvell: armada: fix BL32 extra parameters usage
Update missing code releated to the BL32 payload.
Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
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| #
9935047b |
| 17-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble:
Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration
* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble: ap807: clean-up PLL configuration sequence
ddr: a80x0: add DDR 32-bit mode support
plat: marvell: mci: perform mci link tuning for all mci interfaces
plat: marvell: mci: use more meaningful name for mci link tuning
plat: marvell: a8k: remove wrong or unnecessary comments
plat: marvell: ap807: enable snoop filter for ap807
plat: marvell: ap807: update configuration space of each CP
plat: marvell: ap807: use correct address for MCIx4 register
plat: marvell: add support for PLL 2.2GHz mode
plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
marvell: armada: add extra level in marvell platform hierarchy
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| #
a2847172 |
| 05-Nov-2019 |
Grzegorz Jaszczyk <jaz@semihalf.com> |
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla
marvell: armada: add extra level in marvell platform hierarchy
This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.
Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
show more ...
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