Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration

* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is pr

Merge changes I8f3afbe3,I441e7c69,I2e9465f7,Ib8756cd3,Iebe6ea7c, ... into integration

* changes:
plat/marvell: remove subversion from Marvell make files
drivers/marvell: check if TRNG unit is present
plat/marvell: a8k: move efuse definitions to separate header
plat/marvell/armada: fix TRNG return SMC handling
drivers: marvell: comphy: add rx training on 10G port
plat/marvell/armada: postpone MSS CPU startup to BL31 stage
plat: marvell: armada: a8k: Fix LD selector mask
plat/marvell/armada: allow builds without MSS support
drivers: marvell: misc-dfx: extend dfx whitelist
drivers: marvell: add support for secure read/write of dfx register-set
ddr_phy: use smc calls to access ddr phy registers
drivers: marvell: thermal: use dedicated function for thermal SiPs
drivers: marvell: add thermal sensor driver and expose it via SIP service
fix: plat: marvell: fix MSS loader for A8K family

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plat/marvell/armada: postpone MSS CPU startup to BL31 stage

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes s

plat/marvell/armada: postpone MSS CPU startup to BL31 stage

Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2.
However, (especailly in secure boot mode), some bus attributes should be
changed from defaults before the MSS CPU tries to access shared resources.
This patch starts to use CP MSS SRAM for FW load in both secure and
non-secure boot modes.
The FW loader inserts a magic number into MSS SRAM as an indicator of
successfully loaded FS during the BL2 stage and skips releasing the MSS
CPU from the reset state.
Then, at BL31 stage, the MSS CPU is released from reset following the
call to cp110_init function that handles all the required bus attributes
configurations.

Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>

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Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration

* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble:

Merge changes I80316689,I23cac4fb,If911e7de,I169ff358,I4e040cd5, ... into integration

* changes:
ddr: a80x0: add DDR 32-bit ECC mode support
ble: ap807: improve PLL configuration sequence
ble: ap807: clean-up PLL configuration sequence
ddr: a80x0: add DDR 32-bit mode support
plat: marvell: mci: perform mci link tuning for all mci interfaces
plat: marvell: mci: use more meaningful name for mci link tuning
plat: marvell: a8k: remove wrong or unnecessary comments
plat: marvell: ap807: enable snoop filter for ap807
plat: marvell: ap807: update configuration space of each CP
plat: marvell: ap807: use correct address for MCIx4 register
plat: marvell: add support for PLL 2.2GHz mode
plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic
marvell: armada: add extra level in marvell platform hierarchy

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marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
pla

marvell: armada: add extra level in marvell platform hierarchy

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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