| #
b33772eb |
| 04-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]
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| #
328718f2 |
| 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
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| #
6ce30346 |
| 04-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1783 from thloh85-intel/integration_v2
plat: intel: Add BL2 support for Stratix 10 SoC
|
| #
9d82ef26 |
| 04-Feb-2019 |
Loh Tien Hock <tien.hock.loh@intel.com> |
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scru
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
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