| #
c6b2bb99 |
| 09-Oct-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): update nand driver to enable Linux OS boot" into integration
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| #
6f7f8b18 |
| 29-Jun-2025 |
Girisha Dengi <girisha.dengi@altera.com> |
fix(intel): update nand driver to enable Linux OS boot
Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.
Change-Id: If592680ef359
fix(intel): update nand driver to enable Linux OS boot
Update the nand driver SDR mode with the correct timing
and combo-phy configurations to enable the Linux system
boot.
Change-Id: If592680ef359378574b913b11d466c89389a2606
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
show more ...
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| #
60a15d63 |
| 19-Aug-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): select the DFI interface based on the hand-off data" into integration
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| #
6993598f |
| 28-Jun-2025 |
Girisha Dengi <girisha.dengi@altera.com> |
fix(intel): select the DFI interface based on the hand-off data
Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data
fix(intel): select the DFI interface based on the hand-off data
Select the DFI interface based on the hand-off power
gate enable data, whether NAND or SDMMC controller is
selected based on this data.
Change-Id: I097b7f84874368a5ed265d8fa7fff193f430b245
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
show more ...
|
| #
3393060c |
| 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
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| #
ddaf02d1 |
| 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
show more ...
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