feat(imx93): enable the s401 clock on/off handshake

Enable s401 clock on/off handshake to make sure s401 is in
idle/known status before glock gating.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Rev

feat(imx93): enable the s401 clock on/off handshake

Enable s401 clock on/off handshake to make sure s401 is in
idle/known status before glock gating.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I6cea378ee62a00404cb4078f2e4c24816b43761f

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fix(imx93): reduce the pmic stby off delay

The default PMIC STBY OFF delay is about 78ms, it is too long.
To optimize the system resume latency, reduce the PMIC STBY OFF
delay to 1.5ms, This delay i

fix(imx93): reduce the pmic stby off delay

The default PMIC STBY OFF delay is about 78ms, it is too long.
To optimize the system resume latency, reduce the PMIC STBY OFF
delay to 1.5ms, This delay is large enough to cover the PMIC regulator
voltage ramp up latency when PMIC exit from the STBY mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I184e85282d43a34beac317f90fcd1789fd8184ee

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feat(imx93): optimize power switch acknowledgment timing

The PSW_ACK_CTRL register's CNT_MODE field controls the timing of
power switch acknowledgment during low power mode transitions.

The default

feat(imx93): optimize power switch acknowledgment timing

The PSW_ACK_CTRL register's CNT_MODE field controls the timing of
power switch acknowledgment during low power mode transitions.

The default CNT_MODE value of 0x1 introduces an unnecessary ~1ms
delay when exiting low power modes for A55 cores and cluster.

Set CNT_MODE to 0x0 (instant acknowledgment) for A55 core & cluster
to eliminate unnecessary latency.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I7f72d199ad9cd336fc90dde1dafb7012b08b812f

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feat(imx93): retrieve SoC info from EdgeLock Enclave

Query the EdgeLock Enclave (ELE) during platform setup to obtain
SoC identification information. This enables runtime access to
device-specific d

feat(imx93): retrieve SoC info from EdgeLock Enclave

Query the EdgeLock Enclave (ELE) during platform setup to obtain
SoC identification information. This enables runtime access to
device-specific data such as SoC revision and security state.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I89f10ae02848300e12ff82cf4c5f9f79aa6eaa19

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refactor(imx93): migrate to common GICv3 driver

Enable USE_GIC_DRIVER to leverage the common GICv3 driver
implementation instead of platform-specific GIC initialization code.

This reduces code dupl

refactor(imx93): migrate to common GICv3 driver

Enable USE_GIC_DRIVER to leverage the common GICv3 driver
implementation instead of platform-specific GIC initialization code.

This reduces code duplication and improves maintainability by
reusing the common GIC driver infrastructure.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If2f90692a666b2d25aaccff77ff406f3f880fe0b

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fix(imx93): reduce BL31 limit to reserve DRAM timing area

The DRAM timing parameters are stored at the end of OCRAM region.
Previously, BL31_LIMIT was set to 0x20520000, which overlaps with
this res

fix(imx93): reduce BL31 limit to reserve DRAM timing area

The DRAM timing parameters are stored at the end of OCRAM region.
Previously, BL31_LIMIT was set to 0x20520000, which overlaps with
this reserved area.

Reduce BL31_LIMIT from 0x20520000 to 0x2051C000, reserving the last
16KB of the OCRAM region for DRAM timing storage:

OCRAM layout:
+-------------------+ 0x20480000 (OCRAM_BASE)
| |
+-------------------+ 0x204E0000 (BL31_BASE)
| BL31 |
| (240KB max) |
+-------------------+ 0x2051C000 (BL31_LIMIT)
| DRAM timing |
| (16KB) |
+-------------------+ 0x20520000 (OCRAM_BASE + OCRAM_SIZE)

Introduce BL31_SIZE (256KB) for memory mapping purposes, while
BL31_LIMIT enforces the actual binary size constraint at link time.
This enables the linker to detect potential memory overlap issues
during compilation rather than at runtime.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I0c0466d65ebac7f51e74ea279dadae469bd0e991

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fix(imx93): add null terminator to mmap region array

The mmap_add() API iterates through the memory region array until it
encounters a zero entry. Without a proper null terminator {0}, the
behavior

fix(imx93): add null terminator to mmap region array

The mmap_add() API iterates through the memory region array until it
encounters a zero entry. Without a proper null terminator {0}, the
behavior is undefined.

When TF-A runs on OCRAM, the memory is zeroed by default, masking
this bug. However, when loaded by QNX SPL (which may place TF-A in
non-zeroed memory), the missing terminator causes boot failure.

Add the required {0} terminator to bl_regions[] array.

Signed-off-by: Maximus <maximus.sun@nxp.com>
Change-Id: If7f1313bcb04d97ac760e27984508ba4e6c6c752
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

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fix(imx93): trdc: restrict BLK_CTRL_S_AONMIX to secure world

Configure the TRDC to restrict access to BLK_CTRL_S_AONMIX to secure
world only. So the A55 resume entry in RVBARADDR0 can't be modified

fix(imx93): trdc: restrict BLK_CTRL_S_AONMIX to secure world

Configure the TRDC to restrict access to BLK_CTRL_S_AONMIX to secure
world only. So the A55 resume entry in RVBARADDR0 can't be modified
by untrusted applications.

Change-Id: I498580030d5c893b6d1c1739644eeca9b55c39ec
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>

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Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx

Merge changes I44537ba2,Ia12d3577,I06b3012c,Iec885405,Idab8013a into integration

* changes:
feat(imx8mp): optionally take params from BL2
feat(imx8mn): optionally take params from BL2
feat(imx8mm): optionally take params from BL2
feat(imx93): optionally take params from BL2
feat(imx): add helper to take params from BL2

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refactor(console): consolidate console runtime switch

Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME)
to bl31_main(). This has been done per the recommendation in TF-A
mailin

refactor(console): consolidate console runtime switch

Refactor console_flush() and console_switch_state(CONSOLE_FLAG_RUNTIME)
to bl31_main(). This has been done per the recommendation in TF-A
mailing list. These calls need to be the last calls, after any runtime
initialization has been done, before BL31 exits.

All platforms that override the generic implementation of
bl31_plat_runtime_setup() have been refactored. The console_flush()
and console_switch_state() calls have been removed as they become
part of bl31_main() function.

Any platform that don't need to make any change to the generic (weak)
implementation of bl31_plat_runtime_setup() don't need to override it
in their platforms.

Change-Id: I6d04d6daa9353daeaa7e3df9e9adf6f322a917b8
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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refactor(imx): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A pla

refactor(imx): console runtime switch on bl31 exit

Flush the FIFO before switching to runtime. This is so that there are
no lingering chars in the FIFO when we move to the runtime console.

TF-A plans to refactor the console_Switch_state(CONSOLE_FLAG_RUNTIME)
and console_flush() calls and make them the last calls in bl31_main()
(before BL31 exits). Until then they are being left as the last calls
in bl31_plat_runtime_setup() for testing before refactoring.

This patch affects the Freescale/NXP SoCs imx93, imx8qm and imx8qx.

Change-Id: Iece74579e1d15eeeb8279db0c53d74bce45545bd
Signed-off-by: Salman Nabi <salman.nabi@arm.com>

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