| #
773a310f |
| 16-Sep-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "rustspmc_with_xferlist" into integration
* changes: feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm feat(fvp): update evtlog info in the xferlist's DT_SP
Merge changes from topic "rustspmc_with_xferlist" into integration
* changes: feat(fvp): introduce fvp_stmm_bl2_sp_list.dts for StandaloneMm feat(fvp): update evtlog info in the xferlist's DT_SPMC_MANIFEST entry feat(fvp): move PLAT_ARM_SPMC_SP_MANIFEST_SIZE definition feat(spmd): get spmc manifest from xferlist
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| #
55fd56d7 |
| 03-Sep-2025 |
Yeoreum Yun <yeoreum.yun@arm.com> |
feat(spmd): get spmc manifest from xferlist
When TRANSFER_LIST build option is used, arg0 doesn't pass the SPMC manifest. but it should be passed to load SPMC.
For this, adds the spmc manifest entr
feat(spmd): get spmc manifest from xferlist
When TRANSFER_LIST build option is used, arg0 doesn't pass the SPMC manifest. but it should be passed to load SPMC.
For this, adds the spmc manifest entry in the transfer list with TL_TAG_DT_SPMC_MANIFEST tag and let spmd load the spmc manifest from transfer list.
Change-Id: I3b84c3d8a17bba4ac94afe00e1e19044449360b0 Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
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| #
af4fee04 |
| 10-Feb-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes: feat(spmd): map SPMC manifest region as EL3_PAS feat(fvp): update device tree with load addresses of TOS_FW
Merge changes from topic "mb/tos-fw-config-load-refactor" into integration
* changes: feat(spmd): map SPMC manifest region as EL3_PAS feat(fvp): update device tree with load addresses of TOS_FW config refactor(fvp): rename the DTB info structure member feat(fconf): rename 'ns-load-address' to 'secondary-load-address'
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| #
8c829a92 |
| 07-Feb-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(spmd): map SPMC manifest region as EL3_PAS
Mapped SPMC manifest region as EL3_PAS so that it will get mapped as Root region in RME enabled system otherwise Secure region.
Change-Id: I1af5344d7
feat(spmd): map SPMC manifest region as EL3_PAS
Mapped SPMC manifest region as EL3_PAS so that it will get mapped as Root region in RME enabled system otherwise Secure region.
Change-Id: I1af5344d7516e948d5b3664bcdb94cdfc367cd78 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
28623c10 |
| 08-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix: libc: use long for 64-bit types on aarch64" into integration
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| #
4ce3e99a |
| 25-Aug-2020 |
Scott Branden <scott.branden@broadcom.com> |
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width type
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1 Signed-off-by: Scott Branden <scott.branden@broadcom.com>
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| #
3e1e08b7 |
| 25-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "tegra194-spmd" into integration
* changes: Tegra194: introduce support for `SPD=spmd` Tegra: introduce backend support to compile libfdt Tegra: disable signed compari
Merge changes from topic "tegra194-spmd" into integration
* changes: Tegra194: introduce support for `SPD=spmd` Tegra: introduce backend support to compile libfdt Tegra: disable signed comparison plat: common: include "bl_common.h" from plat_spmd_manifest.c
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| #
cb7b9db1 |
| 20-Jul-2020 |
Varun Wadekar <vwadekar@nvidia.com> |
plat: common: include "bl_common.h" from plat_spmd_manifest.c
This patch includes the bl_common.h from plat_spmd_manifest.c to fix the following compilation errors
<snip> plat/common/plat_spmd_mani
plat: common: include "bl_common.h" from plat_spmd_manifest.c
This patch includes the bl_common.h from plat_spmd_manifest.c to fix the following compilation errors
<snip> plat/common/plat_spmd_manifest.c: In function 'plat_spm_core_manifest_load': plat/common/plat_spmd_manifest.c:130:18: error: implicit declaration of function 'page_align' [-Werror=implicit-function-declaration] 130 | pm_base_align = page_align(pm_base, UP); | ^~~~~~~~~~ plat/common/plat_spmd_manifest.c:130:38: error: 'UP' undeclared (first use in this function); did you mean 'UL'? 130 | pm_base_align = page_align(pm_base, UP); | ^~ | UL plat/common/plat_spmd_manifest.c:130:38: note: each undeclared identifier is reported only once for each function it appears in plat/common/plat_spmd_manifest.c:146:38: error: 'DOWN' undeclared (first use in this function) 146 | pm_base_align = page_align(pm_base, DOWN); | ^~~~ cc1: all warnings being treated as errors <snip>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ib8edb36c6a80a23df2462e708c513c966aab1fef
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| #
3aa2abbb |
| 14-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "SPMD: fix boundary check if manifest is page aligned" into integration
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| #
fdd5f9e6 |
| 08-Jul-2020 |
Manish Pandey <manish.pandey2@arm.com> |
SPMD: fix boundary check if manifest is page aligned
while mapping SPMC manifest page in the SPMD translation regime the mapped size was resolved to zero if SPMC manifest base address is PAGE aligne
SPMD: fix boundary check if manifest is page aligned
while mapping SPMC manifest page in the SPMD translation regime the mapped size was resolved to zero if SPMC manifest base address is PAGE aligned, causing SPMD to abort.
To fix the problem change mapped size to PAGE_SIZE if manifest base is PAGE aligned.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I06cd39dbefaf492682d9bbb0c82b950dd31fb416
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| #
4b0695ac |
| 26-May-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "SPCI is now called PSA FF-A" into integration
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| #
662af36d |
| 07-May-2020 |
J-Alves <joao.alves@arm.com> |
SPCI is now called PSA FF-A
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA
SPCI is now called PSA FF-A
SPCI is renamed as PSA FF-A which stands for Platform Security Architecture Firmware Framework for A class processors. This patch replaces the occurrence of SPCI with PSA FF-A(in documents) or simply FFA(in code).
Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760 Signed-off-by: J-Alves <joao.alves@arm.com>
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| #
c9ff4e47 |
| 13-May-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I35c5abd9,I99e64245 into integration
* changes: SPMD: extract SPMC DTB header size from SPMD SPMD: code/comments cleanup
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| #
23d5ba86 |
| 07-Feb-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: extract SPMC DTB header size from SPMD
Currently BL2 passes TOS_FW_CONFIG address and size through registers to BL31. This corresponds to SPMC manifest load address and size. The SPMC manifest
SPMD: extract SPMC DTB header size from SPMD
Currently BL2 passes TOS_FW_CONFIG address and size through registers to BL31. This corresponds to SPMC manifest load address and size. The SPMC manifest is mapped in BL31 by dynamic mapping. This patch removes BL2 changes from generic code (which were enclosed by SPD=spmd) and retrieves SPMC manifest size directly from within SPMD. The SPMC manifest load address is still passed through a register by generic code.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I35c5abd95c616ae25677302f0b1d0c45c51c042f
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| #
52696946 |
| 16-Apr-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
SPMD: code/comments cleanup
As a follow-up to bdd2596d4, and related to SPM Dispatcher EL3 component and SPM Core S-EL2/S-EL1 component: update with cosmetic and coding rules changes. In addition: -
SPMD: code/comments cleanup
As a follow-up to bdd2596d4, and related to SPM Dispatcher EL3 component and SPM Core S-EL2/S-EL1 component: update with cosmetic and coding rules changes. In addition: -Add Armv8.4-SecEL2 arch detection helper. -Add an SPMC context (on current core) get helper. -Return more meaningful error return codes. -Remove complexity in few spmd_smc_handler switch-cases. -Remove unused defines and structures from spmd_private.h
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I99e642450b0dafb19d3218a2f0e2d3107e8ca3fe
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| #
65808674 |
| 04-May-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "fdt_wrappers_rework" into integration
* changes: arm: fconf: Fix GICv3 dynamic configuration plat/stm32: Implement fdt_read_uint32_default() as a wrapper fdt/wrappers
Merge changes from topic "fdt_wrappers_rework" into integration
* changes: arm: fconf: Fix GICv3 dynamic configuration plat/stm32: Implement fdt_read_uint32_default() as a wrapper fdt/wrappers: Replace fdtw_read_cells() implementation plat/stm32: Use generic fdt_read_uint32_array() implementation fdt/wrappers: Generalise fdtw_read_array()
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| #
ff4e6c35 |
| 26-Mar-2020 |
Andre Przywara <andre.przywara@arm.com> |
fdt/wrappers: Replace fdtw_read_cells() implementation
Our fdtw_read_cells() implementation goes to great lengths to sanity-check every parameter and result, but leaves a big hole open: The size of
fdt/wrappers: Replace fdtw_read_cells() implementation
Our fdtw_read_cells() implementation goes to great lengths to sanity-check every parameter and result, but leaves a big hole open: The size of the storage the value pointer points at needs to match the number of cells given. This can't be easily checked at compile time, since we lose the size information by using a void pointer. Regardless the current usage of this function is somewhat wrong anyways, since we use it on single-element, fixed-length properties only, for which the DT binding specifies the size. Typically we use those functions dealing with a number of cells in DT context to deal with *dynamically* sized properties, which depend on other properties (#size-cells, #clock-cells, ...), to specify the number of cells needed.
Another problem with the current implementation is the use of ambiguously sized types (uintptr_t, size_t) together with a certain expectation about their size. In general there is no relation between the length of a DT property and the bitness of the code that parses the DTB: AArch64 code could encounter 32-bit addresses (where the physical address space is limited to 4GB [1]), while AArch32 code could read 64-bit sized properties (/memory nodes on LPAE systems, [2]).
To make this more clear, fix the potential issues and also align more with other DT users (Linux and U-Boot), introduce functions to explicitly read uint32 and uint64 properties. As the other DT consumers, we do this based on the generic "read array" function. Convert all users to use either of those two new functions, and make sure we never use a pointer to anything other than uint32_t or uint64_t variables directly.
This reveals (and fixes) a bug in plat_spmd_manifest.c, where we write 4 bytes into a uint16_t variable (passed via a void pointer).
Also we change the implementation of the function to better align with other libfdt users, by using the right types (fdt32_t) and common variable names (*prop, prop_names).
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi#n874 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/ecx-2000.dts
Change-Id: I718de960515117ac7a3331a1b177d2ec224a3890 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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| #
bb37363b |
| 13-Mar-2020 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "SPMD: Add support for SPCI_ID_GET" into integration
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| #
ac03ac5e |
| 12-Mar-2020 |
Max Shvetsov <maksims.svecovs@arm.com> |
SPMD: Add support for SPCI_ID_GET
This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the S
SPMD: Add support for SPCI_ID_GET
This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the SPCI component ID as specified in the manifest for secure world requests.
Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
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| #
d95f7a72 |
| 06-Mar-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd-sel2" into integration
* changes: SPMD: add command line parameter to run SPM at S-EL2 or S-EL1 SPMD: smc handler qualify secure origin using booleans SPMD: SPMC
Merge changes from topic "spmd-sel2" into integration
* changes: SPMD: add command line parameter to run SPM at S-EL2 or S-EL1 SPMD: smc handler qualify secure origin using booleans SPMD: SPMC init, SMC handler cosmetic changes SPMD: [tegra] rename el1_sys_regs structure to sys_regs SPMD: Adds partially supported EL2 registers. SPMD: save/restore EL2 system registers.
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| #
033039f8 |
| 25-Feb-2020 |
Max Shvetsov <maksims.svecovs@arm.com> |
SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
Added SPMD_SPM_AT_SEL2 build command line parameter. Set to 1 to run SPM at S-EL2. Set to 0 to run SPM at S-EL1 (pre-v8.4 or S-EL2 is di
SPMD: add command line parameter to run SPM at S-EL2 or S-EL1
Added SPMD_SPM_AT_SEL2 build command line parameter. Set to 1 to run SPM at S-EL2. Set to 0 to run SPM at S-EL1 (pre-v8.4 or S-EL2 is disabled). Removed runtime EL from SPM core manifest.
Change-Id: Icb4f5ea4c800f266880db1d410d63fe27a1171c0 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
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| #
63aa4094 |
| 11-Feb-2020 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0
Merge changes from topic "spmd" into integration
* changes: SPMD: enable SPM dispatcher support SPMD: hook SPMD into standard services framework SPMD: add SPM dispatcher based upon SPCI Beta 0 spec SPMD: add support to run BL32 in TDRAM and BL31 in secure DRAM on Arm FVP SPMD: add support for an example SPM core manifest SPMD: add SPCI Beta 0 specification header file
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| #
0cb64d01 |
| 11-Oct-2019 |
Achin Gupta <achin.gupta@arm.com> |
SPMD: add support for an example SPM core manifest
This patch repurposes the TOS FW configuration file as the manifest for the SPM core component which will reside at the secure EL adjacent to EL3.
SPMD: add support for an example SPM core manifest
This patch repurposes the TOS FW configuration file as the manifest for the SPM core component which will reside at the secure EL adjacent to EL3. The SPM dispatcher component will use the manifest to determine how the core component must be initialised. Routines and data structure to parse the manifest have also been added.
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Change-Id: Id94f8ece43b4e05609f0a1d364708a912f6203cb
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