| 29ae73e3 | 07-Aug-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'pla
Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'plat_mboot_measure_key' function
feat(tc): implement platform function to measure and publish Public Key
feat(auth): measure and publicise the Public Key
feat(fvp): implement platform function to measure and publish Public Key
feat(fvp): add public key-OID information in RSS metadata structure
feat(auth): add explicit entries for key OIDs
feat(rss): set the signer-ID in the RSS metadata
feat(auth): create a zero-OID for Subject Public Key
docs: add details about plat_mboot_measure_key function
feat(measured-boot): introduce platform function to measure and publish Public Key
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| 7e030b37 | 11-Jul-2023 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
fix(errata-abi): added Neoverse N2 to Errata ABI list
added the missing Neoverse N2 flag required for
enabling Neoverse N2 CPU in Errata ABI
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm
fix(errata-abi): added Neoverse N2 to Errata ABI list
added the missing Neoverse N2 flag required for
enabling Neoverse N2 CPU in Errata ABI
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I06c6fa67e2f1ccc053f1b1b9261e189c56f4347a
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| e8027488 | 21-Jun-2023 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
feat(rdn2): enable Neoverse N2 CPU error handling support
Defines N2 CPU RAS error for RD-N2 platform variants. Enables N2 CPU
error handling on RD-N2 platform variants.
Signed-off-by: Omkar Anand
feat(rdn2): enable Neoverse N2 CPU error handling support
Defines N2 CPU RAS error for RD-N2 platform variants. Enables N2 CPU
error handling on RD-N2 platform variants.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: If9378064c41e0d14e6c789c71f8def594f89e220
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| 31d1e4ff | 27-Jun-2023 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
feat(sgi): firmware first error handling for Neoverse N2 CPU
RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1
feat(sgi): firmware first error handling for Neoverse N2 CPU
RD-N2 platform variants have Neoverse N2 CPU that supports RAS
extensions. N2 CPU has error node that captures the faults occurring on
L1, L2 tag and data RAMs. This node captures the error information in
its error records and generates fault handling interrupt on error event.
This patch adds reference implementation to demonstrate firmware-first
error handling of 1-bit CE that occur on CPU. On error event the error
handler reads the error records and ELx context information and forwards
it to secure partition. Secure partition creates a CPER record from this
error information. Finally the handler notifies the OS about the RAS
error using the SDEI notification mechanism.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I769550efee10b9a3d89056bca4bfeb2db4708998
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| f1e4a28d | 21-Jul-2023 |
Omkar Anand Kulkarni <omkar.kulkarni@arm.com> |
feat(arm): enable FHI PPI interrupt to report CPU errors
To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framewor
feat(arm): enable FHI PPI interrupt to report CPU errors
To handle the core corrected errors in the firmware, the FHI PPI
interrupt has to be enabled on all the cores. At boot, when the RAS
framework is initialized, only primary core is up and hence core FHI PPI
interrupt is enabled only on primary core. This patch adds support to
configure and enable core FHI interrupt for all the secondary cores as
part of their boot sequence.
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I4b25152cb498fe975b9c770babb25aa9e01f9656
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| eee9fb02 | 12-Jul-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(tc): implement platform function to measure and publish Public Key
Implemented 'plat_mboot_measure_key' platform function for TC platform
to measure and publicise the public key information via
feat(tc): implement platform function to measure and publish Public Key
Implemented 'plat_mboot_measure_key' platform function for TC platform
to measure and publicise the public key information via RSS.
Change-Id: I10d90e921b135e729d5450d5a7468d0598072e60
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| db55d23d | 11-Apr-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): implement platform function to measure and publish Public Key
Implemented 'plat_mboot_measure_key' platform function for FVP platform
to measure and publish the public key information via
feat(fvp): implement platform function to measure and publish Public Key
Implemented 'plat_mboot_measure_key' platform function for FVP platform
to measure and publish the public key information via RSS.
Change-Id: I0c9d6d6ac3650a939437e9331ed3c9246f242830
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| bfbb1cba | 11-Apr-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(fvp): add public key-OID information in RSS metadata structure
Added public key-OID information in the RSS metadata structure.
Change-Id: I5ee5d41519980091296deaa1882fdfe9ae6766c0
Signed-off-b
feat(fvp): add public key-OID information in RSS metadata structure
Added public key-OID information in the RSS metadata structure.
Change-Id: I5ee5d41519980091296deaa1882fdfe9ae6766c0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 60784c3e | 09-May-2023 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
chore(fvp): add Aarch32 Cortex-A53 to the build
Change-Id: I493893d38d2db80e2c4d2efcf832c712a9abe5a8
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
| cd91aa17 | 20-Jul-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(fvp): adjust BL2 maximum size as per total SRAM size" into integration |
| 965aacea | 19-Jul-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(fvp): adjust BL2 maximum size as per total SRAM size
Adjusted BL2 maximum size as per total SRAM size.
Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Man
fix(fvp): adjust BL2 maximum size as per total SRAM size
Adjusted BL2 maximum size as per total SRAM size.
Change-Id: Ic3b398574a17e8a784e7c4dbe3fe69d1fb2b5e16
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 4d0b6632 | 24-Mar-2023 |
Maksims Svecovs <maksims.svecovs@arm.com> |
feat(mte): adds feature detection for MTE_PERM
Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.
Change-Id: If24b42
feat(mte): adds feature detection for MTE_PERM
Adds feature detection for v8.9 feature FEAT_MTE_PERM. Adds respective
ID_AA64PFR2_EL1 definitions and ENABLE_FEAT_MTE_PERM define.
Change-Id: If24b42f1207154e639016b0b840b2d91c6ee13d4
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 80c2c374 | 19-Jul-2023 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "fix(spmd): perform G0 interrupt acknowledge and deactivation" into integration |
| c5ce48f5 | 17-Jul-2023 |
laurenw-arm <lauren.wehrmeister@arm.com> |
refactor(tc): move all plat tests in test makefile
Moving all PLATFORM_TESTS into platform test makefile
Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <laur
refactor(tc): move all plat tests in test makefile
Moving all PLATFORM_TESTS into platform test makefile
Change-Id: I31821e9e69d916d12ae4c804df26f07fb523c835
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| 6c91fc44 | 12-Jul-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
fix(spmd): perform G0 interrupt acknowledge and deactivation
Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrup
fix(spmd): perform G0 interrupt acknowledge and deactivation
Prior to delegating handling of Group0 secure interrupt to platform
handler, SPMD framework must acknowledge the highest pending interrupt.
Moreover, once the platform has handled the interrupt successfully,
SPMD must deactivate the interrupt.
The rationale behind this decision is SPMD framework is well suited to
perform interrupt management at GIC boundary while the platform handler
is well equipped to deal with the device interface related to the
interrupt.
This patch also fixes a bug in the error code returned upon invocation
of FFA_EL3_INTR_HANDLE from normal world.
Change-Id: If8fef51899e25f966038cc01ec58c84ee25e88eb
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
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| cb6b7505 | 14-Jul-2023 |
laurenw-arm <lauren.wehrmeister@arm.com> |
refactor(tc): print RSS interface test PSA status
Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tes
refactor(tc): print RSS interface test PSA status
Adding PSA status to print statement upon failing communication
initialization, non-volatile counter, and rotpk read interface calls in
platform_tests.
Change-Id: Ia949cc2d18e93efb68f663d0c4e5500ca9021a94
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| 00b7e0bf | 13-Jun-2023 |
laurenw-arm <lauren.wehrmeister@arm.com> |
test(tc): test for AP/RSS interface for ROTPK
Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.
Enabled by PLATFORM_TEST=r
test(tc): test for AP/RSS interface for ROTPK
Adding new test for AP/RSS interface for reading ROTPK for
each 3 types of ROTPKs for: CCA, secure, and non-secure firmware.
Enabled by PLATFORM_TEST=rss-rotpk.
Update to print output when AP/RSS interface platform tests
pass to be able to reuse expect script functionality in CI.
Change-Id: Icc50b090e18a272378751fda104d209738b5b70c
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
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| 2503c8f3 | 13-Jul-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "build(fpga): remove a710 from fpga build" into integration |
| 9b81d117 | 13-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "master" into integration
* changes:
fix(tc): rename macro to match PSA spec
fix(tc): Correct return type |
| e0ef05bb | 28-Jun-2023 |
Wing Li <wingers@google.com> |
fix(fvp): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR
fix(fvp): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ia0fb1e68af9320370325642b17c4569e9580aa3a
Signed-off-by: Wing Li <wingers@google.com>
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| bd596a10 | 06-Jul-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
build(fpga): remove a710 from fpga build
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framewor
build(fpga): remove a710 from fpga build
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framework can cause the size to grow and thus causing build
failure on bl31 size. This as of today is blocking us from
merging most of our changes as it will introduce a CI failure.
As an workaround we try to just reduce the arm_fpga build by a710
platform, we have a715 and a720 which should be ok I think.
Once everyone are available for further discussion we could revert this
change back and discuss further whats the right approach.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I96a821e10aaecf04db7407fb2df38012839bfb94
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| da36a232 | 06-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mb/mb-rss-refactor" into integration
* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS
Merge changes from topic "mb/mb-rss-refactor" into integration
* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS driver standalone for Measured Boot
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| 1fc20d7f | 30-Jun-2023 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(tc): rename macro to match PSA spec
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I583
fix(tc): rename macro to match PSA spec
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I5837fea552e6fe18a203412eb90d41e2f90ad6f1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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| b0542b58 | 04-Jul-2023 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(tc): Correct return type
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-te
fix(tc): Correct return type
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-tests-failing bug.
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: Ief55fe15c437c87dac1d03419a8e148f5d864b8d
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| 7b0c95ab | 25-May-2023 |
Werner Lewis <werner.lewis@arm.com> |
fix(n1sdp): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts ac
fix(n1sdp): configure platform specific secure SPIs
Previous implementation used common CSS interrupts, which do not match
the N1SDP platform interrupt map. Updated to configure Secure
interrupts according to the N1SDP TRM and InfraSYSDESIGN4.0
specification. Additionally, unused definitions from legacy interrupt
configuration are removed.
Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I3dd4bcd4875e138057c62d937572d446b8f88471
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