feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detaile

feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detailed steps are documented as comments in the relevant source
files introduced in this patch.

Change-Id: I97737c66649f6e49840fa0bdf2e0af4fb6b08fc7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(css): initialise generic timer early in the boot

Initialize generic delay timer to enable its use to insert delays
in execution paths as required.

Change-Id: I52232796f20d9692f0115d5e5395451a5

feat(css): initialise generic timer early in the boot

Initialize generic delay timer to enable its use to insert delays
in execution paths as required.

Change-Id: I52232796f20d9692f0115d5e5395451a54b489c6
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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Merge changes I509b7bc5,Ibd36ea5c into integration

* changes:
fix(fconf): boot fails using ARM_ARCH_MINOR=8
fix(libc): add memcpy_s source file to libc_asm mk

fix(fconf): boot fails using ARM_ARCH_MINOR=8

When building TF-A (with SPMD support) with ARM_ARCH_MAJOR=8/
ARCH_ARCH_MINOR=8 options, this forces the -march=armv8.8-a compiler
option. In this condi

fix(fconf): boot fails using ARM_ARCH_MINOR=8

When building TF-A (with SPMD support) with ARM_ARCH_MAJOR=8/
ARCH_ARCH_MINOR=8 options, this forces the -march=armv8.8-a compiler
option. In this condition, the compiler optimises statement [1] into
a store pair to an unaligned address resulting to a supposedly alignment
fault. With -march=armv8.7-a and earlier the compiler resolves with a
memcpy. Replacing this line by an explicit memcpy masks out the issue.
Prefer using the plain struct uuid in place of the uuid_helper union
for further clarity.

[1] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/
plat/arm/common/fconf/arm_fconf_sp.c?h=v2.10#n77

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I509b7bc50c7c4a894885d24dc8279d0fe634e8f2

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Merge changes from topic "plat_gpt_setup" into integration

* changes:
feat(arm): move GPT setup to common BL source
feat(arm): retrieve GPT related data from platform
refactor(arm): rename L0/

Merge changes from topic "plat_gpt_setup" into integration

* changes:
feat(arm): move GPT setup to common BL source
feat(arm): retrieve GPT related data from platform
refactor(arm): rename L0/L1 GPT base macros

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feat(cpufeat): add feature detection for FEAT_CSV2_3

This feature provides support to context save the
SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation
of FEAT_CSV2_2. FEAT_CSV2_3 is sup

feat(cpufeat): add feature detection for FEAT_CSV2_3

This feature provides support to context save the
SCXTNUM_ELx register. FEAT_CSV2_3 implies the implementation
of FEAT_CSV2_2. FEAT_CSV2_3 is supported in AArch64 state only
and is an optional feature in Arm v8.0 implementations.

This patch adds feature detection for v8.9 feature FEAT_CSV2_3,
adds macros for ID_AA64PFR0_EL1.CSV2 bits [59:56] for detecting
FEAT_CSV2_3 and macro for ENABLE_FEAT_CSV2_3.

Change-Id: Ida9f31e832b5f11bd89eebd6cc9f10ddad755c14
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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feat(arm): move GPT setup to common BL source

As of now, GPT setup is being handled from BL2 for plat/arm platforms.
However, for platforms having a separate entity to load firmware images,
it is po

feat(arm): move GPT setup to common BL source

As of now, GPT setup is being handled from BL2 for plat/arm platforms.
However, for platforms having a separate entity to load firmware images,
it is possible for BL31 to setup the GPT. In order to address this
concern, move the GPT setup implementation from arm_bl2_setup.c file to
arm_common.c. Additionally, rename the API from arm_bl2_gpt_setup to
arm_gpt_setup to make it boot stage agnostic.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I35d17a179c8746945c69db37fd23d763a7774ddc

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feat(arm): retrieve GPT related data from platform

For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the G

feat(arm): retrieve GPT related data from platform

For RME-enabled platforms, initializing L0 and L1 tables and enabling
GPC checks is necessary. For systems using BL2 to load firmware images,
the GPT initialization has to be done in BL2 prior to the image load.
The common Arm platform code currently implements this in the
"arm_bl2_plat_gpt_setup" function, relying on the FVP platform's
specifications (PAS definitions, GPCCR_PPS, and GPCCR_PGS).

Different Arm platforms may have distinct PAS definitions, GPCCR_PPS,
GPCCR_PGS, L0/L1 base, and size. To accommodate these variations,
introduce the "plat_arm_get_gpt_info" API. Platforms must implement
this API to provide the necessary data for GPT setup on RME-enabled
platforms. It is essential to note that these additions are relevant to
platforms under the plat/arm hierarchy that will reuse the
"arm_bl2_plat_gpt_setup" function.

As a result of these new additions, migrate data related to the FVP
platform to its source and header files.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I4f4c8894c1cda0adc1f83e7439eb372e923f6147

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refactor(arm): rename L0/L1 GPT base macros

In accordance with common naming conventions, macros specifying the base
address of a region typically use the prefix "BASE" combined with the
region name

refactor(arm): rename L0/L1 GPT base macros

In accordance with common naming conventions, macros specifying the base
address of a region typically use the prefix "BASE" combined with the
region name, rather than "ADDR_BASE."

Currently, the macros defining the base addresses for L0 and L1 GPT
tables within `arm_def.h` are named "ARM_L0_GPT_ADDR_BASE" and
"ARM_L1_GPT_ADDR_BASE" respectively. To adhere to the established naming
convention, rename these macros as "ARM_L1_GPT_BASE" and
"ARM_L0_GPT_BASE" respectively.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: Ibd50a58a1f63ba97d2df141f41a21a89ef97d6fb

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feat(arm): add COT_DESC_IN_DTB option for CCA CoT

Add support for BL2 to get the CCA chain of trust description
through the Firmware Configuration Framework (FCONF). This makes
it possible to export

feat(arm): add COT_DESC_IN_DTB option for CCA CoT

Add support for BL2 to get the CCA chain of trust description
through the Firmware Configuration Framework (FCONF). This makes
it possible to export the part of the CCA chain of trust enforced
by BL2 in BL2's configuration file (TB_FW_CONFIG DTB file). BL2
will parse it when setting up the platform.

This feature can be enabled through the COT_DESC_IN_DTB=1 option.
The default behaviour (COT_DESC_IN_DTB=0) remains to hard-code
the CCA CoT into BL2 image.

Change-Id: Iec4f623d5e42b7c166beeb3ad6b35d918969f7e2
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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feat(fvp): add CCA CoT in DTB support

Adding support for CCA CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file
in DTB format. With this,

feat(fvp): add CCA CoT in DTB support

Adding support for CCA CoT in DTB. This makes it possible for BL2
to retrieve its chain of trust description from a configuration file
in DTB format. With this, the CoT description may be updated without
rebuilding BL2 image. This feature can be enabled by building BL2
with COT_DESC_IN_DTB=1 and COT=cca. The default behaviour remains to
embed the CoT description into BL2 image.

Change-Id: I5912aad5ae529281a93a76e6b8f4b89d867445fe
Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>

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Merge "refactor(juno): move plat_def_uuid_config to fiptool" into integration

fix(rotpk): move rotpk definitions out of arm_def.h

The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing t

fix(rotpk): move rotpk definitions out of arm_def.h

The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing them to avoid a direct dependency on arm_def.h. For a clean
platform port of arm_def.h, none of the source files should directly
include arm_def.h; instead, they should include the platform header
which would indirectly include the required definitions.

Presently, the rotpk module has a source file that directly includes
arm_def.h. This could lead to compilation issues if the platform
incorporating the rotpk module has a separate implementation of some or
all of the definitions in arm_def.h file. To address this, move the
relevant definitions out of arm_def.h and into rotpk_def.h.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I9e8b0d319391f9a167af5c69a7b2d42ac488e7b4

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refactor(juno): move plat_def_uuid_config to fiptool

The same was done for other platforms: stm32mp1, tc before in
commit 034a2e3ef8a9e8e58f7cb7fab6db4ee60b2f9c29 ('refactor(fiptool):
move plat_fipt

refactor(juno): move plat_def_uuid_config to fiptool

The same was done for other platforms: stm32mp1, tc before in
commit 034a2e3ef8a9e8e58f7cb7fab6db4ee60b2f9c29 ('refactor(fiptool):
move plat_fiptool.mk to tools')

Additionally this will make ignore generated files:

Untracked files:
plat/arm/board/juno/fip/plat_def_uuid_config.d
plat/arm/board/juno/fip/plat_def_uuid_config.o

Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
Change-Id: Ia5f1082fcd6d9dfc0be012759493e61ddb869956

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fix(sgi): apply workarounds for N2 CPU erratum

For RD-N2 and variant platforms, enable workarounds available for the
N2 CPU erratum.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id

fix(sgi): apply workarounds for N2 CPU erratum

For RD-N2 and variant platforms, enable workarounds available for the
N2 CPU erratum.

Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Ib0240f56813a913309e5a6a1902e2990979e9617

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feat(rdn2): update power message value to 0

Standalone MM used by RD-N2 platfrom does not have power messaging
support. Set the value to 0.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Ch

feat(rdn2): update power message value to 0

Standalone MM used by RD-N2 platfrom does not have power messaging
support. Set the value to 0.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Icdb16ea1976ce751071ce3df0e4bd86f3fb8ab8b

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fix(tc): guard PSA crypto headers under TF-M test-suite define

The inclusion of PSA crypto headers is specifically required
during the building of TF-M test-suite platform tests for TC2.
Hence guard

fix(tc): guard PSA crypto headers under TF-M test-suite define

The inclusion of PSA crypto headers is specifically required
during the building of TF-M test-suite platform tests for TC2.
Hence guarded the inclusion of these headers under the define
PLATFORM_TEST_TFM_TESTSUITE.

Change-Id: Ia5dcadb93f308d2248d9768d373a87316ceb983c
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(tc): provide a mock mbedtls-random generation function

Simulated the utilization of an external RNG through the
MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG configuration option in mbedTLS.
Consequently, an

feat(tc): provide a mock mbedtls-random generation function

Simulated the utilization of an external RNG through the
MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG configuration option in mbedTLS.
Consequently, an implementation of mbedtls_psa_external_get_random()
is provided. Given the absence of actual external RNG support,
we provide a mock implementation by utilizing the system counter to
fill the the buffer to provide a random number, specifically tailored
for the use exclusively within the TF-M testsuite.
While this method is not ideal for generating random numbers,
alternatives like the 'rand' library function are not feasible due to
lack of support in TF-A. Additionally, the architectural 'rand'
instruction is not viable, as it is only supported for platforms with
Armv8.5-a+ architecture as an optional feature.
mbedtls_psa_external_get_random() function comes into play during the
exportation of the public portion of the delegated attestation key.

This helps in using mbedTLS-3.4.1 for running the delegated attestation
tests on TC platform.

Change-Id: Ifcf4e3231aad93595e00c353a4b0c606c0ef9fc2
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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feat(ff-a): update FF-A version to v1.2

Bump the required FF-A version in framework and manifests to v1.2 as
upstream feature development goes.

Signed-off-by: Kathleen Capella <kathleen.capella@arm

feat(ff-a): update FF-A version to v1.2

Bump the required FF-A version in framework and manifests to v1.2 as
upstream feature development goes.

Signed-off-by: Kathleen Capella <kathleen.capella@arm.com>
Change-Id: I09d936d4aad89965cfd13f58741d647223b63a34

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Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add su

Merge changes from topic "ns/spmc_at_el3" into integration

* changes:
feat(rdn2): add dts for secure partition
feat(el3-spmc): synchronize access to the s-el0 sp context
feat(el3-spmc): add support to map S-EL0 SP device regions
feat(el3-spmc): add support to map S-EL0 SP memory regions
feat(el3-spmc): add support for FFA_MEM_PERM_GET and SET ABIs
feat(el3-spmc): add support to setup S-EL0 context

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feat(rdn2): add dts for secure partition

This patch adds dts for Standalone MM used as S-EL0 SP on RD-N2
platform.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nish

feat(rdn2): add dts for secure partition

This patch adds dts for Standalone MM used as S-EL0 SP on RD-N2
platform.

Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: I9f1a6825d43f8be1c4bdeb98d9d7267b595e2b76

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feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag

Neoverse reference design platforms include a system level cache in the
interconnect and that is the last level cache. So enable the build flag
'

feat(neoverse): enable NEOVERSE_Nx_EXTERNAL_LLC flag

Neoverse reference design platforms include a system level cache in the
interconnect and that is the last level cache. So enable the build flag
'NEOVERSE_Nx_EXTERNAL_LLC' for all the Neoverse reference design
platforms.

Change-Id: I813b3ef7ea7dc4e335b44a88e019d8c56f05f4ac
Signed-off-by: Nuno Lopes <nuno.lopes@arm.com>

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Merge changes from topic "mb/deprecate-rss-for-fvp" into integration

* changes:
refactor(fvp): remove RSS usage
refactor(rss)!: remove PLAT_RSS_NOT_SUPPORTED build option

fix(sgi): reduce cper buffer carveout size

Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1f

fix(sgi): reduce cper buffer carveout size

Reduce the size of the CPER buffer as it is overlapping with SP's heap
region.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Iaea75a1ffb50ecf0223594fe8bffcebc16da7eab

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fix(sgi): increase BL31 carveout size

With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.

Increase the size by 16K.

Signed-of

fix(sgi): increase BL31 carveout size

With SPMC at el3 enabled on rdn2cfg2 configuration BL31 needs more
memory region to accommodate increased xlat table size.

Increase the size by 16K.

Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
Change-Id: Ib235fe35d53a9b85a5ce0a29f2ec4cc3bd85ded9

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