| 9c11ed7e | 22-Dec-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(arm): support FW handoff b/w BL1 & BL2
Leverage the framework between BL1 and BL2. Migrate all handoff structures to the TL.
Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb Signed-off-by:
feat(arm): support FW handoff b/w BL1 & BL2
Leverage the framework between BL1 and BL2. Migrate all handoff structures to the TL.
Change-Id: I79ff3a319596b5656184cde10b5204b10a4d03bb Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 6a4da290 | 04-Jan-2024 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(bl1): clean up bl2 layout calculation
Layout calculation is spread out between core BL1 logic and common platform code. Relocate these into common platform code so they are organised logica
refactor(bl1): clean up bl2 layout calculation
Layout calculation is spread out between core BL1 logic and common platform code. Relocate these into common platform code so they are organised logically.
Change-Id: I8b05403e41b800957a0367316cecd373d10bb1a4 Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| a5566f65 | 01-Dec-2023 |
Harrison Mutai <harrison.mutai@arm.com> |
feat(arm): support FW handoff b/w BL2 & BL31
Add support for the firmware handoff framework between BL2 and BL31. Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes in recent m
feat(arm): support FW handoff b/w BL2 & BL31
Add support for the firmware handoff framework between BL2 and BL31. Create a transfer list in trusted SRAM, leveraging the larger SRAM sizes in recent models. Load the HW_CONFIG as a TE along with entry point parameters for BL31 execution.
Change-Id: I7c4c6e8353ca978a13520fb3e15fb2803f0f1d0e Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| 9a31b68b | 26-Apr-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(tc): missing device regions in spmc manifest" into integration |
| 5e471120 | 24-Apr-2024 |
J-Alves <joao.alves@arm.com> |
fix(tc): missing device regions in spmc manifest
Signed-off-by: J-Alves <joao.alves@arm.com> Change-Id: I847c9ec13c3d40dd9de8cf374a81fc6d23a8864c |
| 8d6fb77a | 31-Dec-2023 |
Rohit Mathew <Rohit.Mathew@arm.com> |
refactor(neoverse-rd): remove soc_css.mk from common makefile
The soc_css.mk file within the plat/arm/soc module currently implements initialization functions for the PCIe controller and NIC400 with
refactor(neoverse-rd): remove soc_css.mk from common makefile
The soc_css.mk file within the plat/arm/soc module currently implements initialization functions for the PCIe controller and NIC400 within the SOC specification. However, as none of the Neoverse reference design platforms necessitate the initialization of PCIe or NIC400, remove the soc_css.mk from the common makefile.
Additionally, empty initialization functions for PCIe and NIC400 are added to satisfy the requirements of the plat/arm common code, which expects these functions to be present.
Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com> Change-Id: Ia431af62f48fc224962d64902dd3acfbf0b93935
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| a965d73f | 26-Feb-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): unify GIC SPI range macros
The existing macros representing GIC SPI minimum and maximum for multichip platforms lack a consistent naming convention. To address this, establish
refactor(neoverse-rd): unify GIC SPI range macros
The existing macros representing GIC SPI minimum and maximum for multichip platforms lack a consistent naming convention. To address this, establish the convention "NRD_CHIP<x>_SPI_MIN" and "NRD_CHIP<x>_SPI_MAX" for use across all Neoverse Reference Design multichip platforms.
Furthermore, extend this naming convention to RD-N2-Cfg2 and introduce similar macros.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Idca2a8c66579f05e712e3b6e95204fedc122cf23
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| a0bd6198 | 19-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file
Consolidate and organize platform port definitions within the nrd_plat_arm_def2.h file. Remove direct references to addresses with correspond
refactor(neoverse-rd): clean-up nrd_plat_arm_def2.h file
Consolidate and organize platform port definitions within the nrd_plat_arm_def2.h file. Remove direct references to addresses with corresponding RoS or CSS definitions.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ic43cff90d2cf45760b3f808732754cf7c05a814a
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| 301c0174 | 03-Apr-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value t
feat(neoverse-rd): disable SPMD_SPM_AT_SEL2 for N2/V2 platforms
SPMD_SPM_AT_SEL2 is enabled by default for platforms. As the platforms based on N2/V2 CPUs don't use SPMD_SPM_AT_SEL2, set its value to 0.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ib503c5552e2b8fee928b2392ba40805664d857d7
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| 2cfedfad | 02-Apr-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(rdn2): enable AMU if present on the platform
Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the feature is implemented on the platform. This would ensure that lower ELs could a
feat(rdn2): enable AMU if present on the platform
Set build-option ENABLE_FEAT_AMU to 2 so that AMU is enabled if the feature is implemented on the platform. This would ensure that lower ELs could access system registers relevant to AMU without causing a trap to EL3.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ic9aa435af54eddacdaa49e69f25893ddaa977e3e
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| 3a5b3753 | 30-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(rdn2): enable MTE2 if present on the platform
MTE2 is an optional feature that could be part of platforms based on Arm V8.5 or above. If this feature is implemented on the platform, lower ELs c
feat(rdn2): enable MTE2 if present on the platform
MTE2 is an optional feature that could be part of platforms based on Arm V8.5 or above. If this feature is implemented on the platform, lower ELs could potentially access the featre registers leading EL3 traps. Therefore, set MTE2 build option to '2' to enable the feature only if its implemented on the platform.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I97c341ac38485937eb18ce9bdcffec26c0e5e76d
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| c396c823 | 26-Feb-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): move defines out of platform_def.h
Presently, the second generation platforms have direct references to CSS and ROS specific addresses within RD-N2's platform header file (pla
refactor(neoverse-rd): move defines out of platform_def.h
Presently, the second generation platforms have direct references to CSS and ROS specific addresses within RD-N2's platform header file (platform_def.h). Moreover, there are platform port specific macros defined within platform_def.h To enhance organization and appropriateness, relocate these definitions to nrd_css_def2.h, nrd_ros_def2.h and nrd_arm_platform_def1.h files accordingly. Reuse these definitions within the platform_def.h files as needed.
Additionally, remove reference to the unused PLAT_ARM_GICC_BASE macro from the individual platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I9a237c3ae28d7e209188e2c37c8494b4a420ee83
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| 7f693bd9 | 26-Feb-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2
In the current setup, the base and size of the ROM, SRAM, and DRAM2 regions are directly defined in the nrd_fw_def2.h file for N2 CPU based
refactor(neoverse-rd): add defines for ROM, SRAM and DRAM2
In the current setup, the base and size of the ROM, SRAM, and DRAM2 regions are directly defined in the nrd_fw_def2.h file for N2 CPU based platforms. To enhance modularity and appropriateness, introduce macros for these definitions in the respective css file (nrd_css_def2.h). While the maximum sizes for ROM, SRAM, and DRAM2 are specified in the css specification, the actual implementation sizes may vary. Consequently, relocate the size macros to the platform-specific platform_def.h file for individual platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I30988bf63cf942f68188a70697cc43cb6af96a9c
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| 947e7872 | 19-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): define naming convention for RoS macros
As part of the refactoring for the second generation platforms, introduce a naming convention for macros within nrd_ros_def2.h and nrd_
refactor(neoverse-rd): define naming convention for RoS macros
As part of the refactoring for the second generation platforms, introduce a naming convention for macros within nrd_ros_def2.h and nrd_ros_fw_def2.h. All macros, except those related to page table entries, must adhere to the format NRD_ROS_<name>. Page table entry macros are handled separately and are not part of this patch.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ifcdc30b1c80b9848b793de2013095fc98d57bec6
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| 069bad71 | 18-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): define naming convention for CSS macros
As part of the refactoring for the second generation of platforms, introduce a naming convention for macros within nrd_css_def2.h and n
refactor(neoverse-rd): define naming convention for CSS macros
As part of the refactoring for the second generation of platforms, introduce a naming convention for macros within nrd_css_def2.h and nrd_css_fw_def2.h. All macros, except those related to page table entries, must adhere to the format NRD_CSS_<name>. Page table entry macros are handled separately and are not part of this patch.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ib168320e12f06cd034342c011909896de463ab27
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| 37f59e4e | 18-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
There are two macros that define ROS device memory map range and attributes - one for local chip and the other for remote chip
refactor(neoverse-rd): refactor mmap macro for RoS device memory region
There are two macros that define ROS device memory map range and attributes - one for local chip and the other for remote chip. Refactor these two macros into a single macro that uses the chip ID to identify the local or the remote chip.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I58eb65c2f046b6074f848f1448cd10a7dcc37f74
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| 9f1ba0af | 18-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
There are two macros that define CSS device memory map range and attributes - one for local chip and the other for remote chip
refactor(neoverse-rd): refactor mmap macro for CSS device memory region
There are two macros that define CSS device memory map range and attributes - one for local chip and the other for remote chip. Refactor these two macros into a single macro that uses the chip ID to identify the local or the remote chip. While at it, rename the macro that defines the memory map range and attributes for the remote shared RAM region.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ieddd5c81f6261490dbacb97160858903e56d327a
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| edd480d9 | 18-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): set mmap naming convention
Presently, for the second generation platforms based on the N2 CPU, macros related to page table entries lack a consistent naming convention. This a
refactor(neoverse-rd): set mmap naming convention
Presently, for the second generation platforms based on the N2 CPU, macros related to page table entries lack a consistent naming convention. This absence may lead to potential mix-ups, such as css definitions in soc files, and can contribute to decreased code clarity. To address this, establish the following naming convention:
- NRD_CSS_<name>_MMAP for CSS related page table entries - NRD_ROS_<name>_MMAP for ROS related page table entries
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I7bf1f9b0ddfd0444c802a23143de6a163f127731
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| 4d4763f7 | 26-Feb-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention
Header files for N2 CPU based platforms currently use "2" as a suffix. Rename the common source file, nrd_plat_v2.c used by these
refactor(neoverse-rd): rename nrd_plat_v2.c to align with convention
Header files for N2 CPU based platforms currently use "2" as a suffix. Rename the common source file, nrd_plat_v2.c used by these platforms to nrd_plat2.c to align with this convention.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I36b138a0a4dff8087e52f0f2cbc21abc03a793ad
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| 13e7d35c | 18-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
Continuing the refactoring of the various definition for platforms based on N2/V2 CPU, refactor the definitions in the nrd_soc_css_def_v2.h
refactor(neoverse-rd): refactor nrd_soc_css_def_v2.h file
Continuing the refactoring of the various definition for platforms based on N2/V2 CPU, refactor the definitions in the nrd_soc_css_def_v2.h file into the following files as appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions - nrd_plat_arm_def2.h: includes platform port related definitions
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: Ib447e67a0a42722735297b27b7f5017bc146156c
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| d26dae7c | 18-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
Continuing the refactoring of the various definitions for the second generation platforms based on the N2/V2 CPU, refactor the definiti
refactor(neoverse-rd): refactor nrd_soc_platform_def_v2.h file
Continuing the refactoring of the various definitions for the second generation platforms based on the N2/V2 CPU, refactor the definitions in the nrd_soc_platform_def_v2.h file into the following files as appropriate.
- nrd_ros_def2.h: includes RoS hardware related definitions - nrd_ros_fw_def2.h: includes RoS firmware related definitions - nrd_plat_arm_def2.h: includes platform port related definitions
RoS (Rest Of System) is used to refer to the part of the reference design platform that excludes CSS. The file inclusions in the platform_def.h file of the platforms have been updated accordingly.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I393e6f4a84be45f1781ea281bd55fa813803f6db
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| 01a27ecc | 26-Feb-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): refactor nrd_base_platform_def.h
The nrd_base_platform_def.h file includes CSS, RoS, firmware and platform port related definitions. This approach of consolidating the various
refactor(neoverse-rd): refactor nrd_base_platform_def.h
The nrd_base_platform_def.h file includes CSS, RoS, firmware and platform port related definitions. This approach of consolidating the various definitions for multiple generation of platforms into the nrd_base_platform_def.h file is not scaling well.
So in preparation of moving away from the use of nrd_base_platform_def.h file for the second generation platforms based on N2/V2 CPUs, split the definitions in this file into multiple include files. The new files into which the definitions are refactored are -
- nrd_css_def2.h: includes CSS hardware related definitions - nrd_css_fw_def2.h: includes CSS firmware related definitions - nrd_ros_fw_def2.h: includes RoS firmware related definitions - nrd_plat_arm_def2.h: includes platform port elated definitions
RoS (Rest Of System) is used to refer to the part of the reference design platform that excludes CSS. The definitions that are only relavant to the aforementioned platforms have been refactored from the nrd_base_platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I45f680857328fa77f0977897490b225bdb29efe4
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| a6b8d7bb | 17-Mar-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
refactor(neoverse-rd): header files for second generation platforms
Presently, platforms such as RD-N2, RD-N2-Cfg1, RD-N2-Cfg2 and RD-V2 utilize nrd_soc_platform_def_v2.h and nrd_soc_css_def_v2.h fo
refactor(neoverse-rd): header files for second generation platforms
Presently, platforms such as RD-N2, RD-N2-Cfg1, RD-N2-Cfg2 and RD-V2 utilize nrd_soc_platform_def_v2.h and nrd_soc_css_def_v2.h for all css and soc-related defines. So move these two header files into a new directory named 'nrd2'. This new directory will serve as the container of header files that are specific to the former stated platforms.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com> Change-Id: I51ba0944dea91ae81e1840947d2e9af9b28d561d
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| 78b79395 | 23-Apr-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(rdn1edge): remove RD-N1-Edge from deprecated list
As RD-N1-Edge is not planned to be deprecated in the upcoming release cycles, remove it from the deprecated list.
Change-Id: I6af06e7bd162747a
feat(rdn1edge): remove RD-N1-Edge from deprecated list
As RD-N1-Edge is not planned to be deprecated in the upcoming release cycles, remove it from the deprecated list.
Change-Id: I6af06e7bd162747aab72384185951d218b388ed3 Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
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| f104eecd | 23-Apr-2024 |
Rohit Mathew <rohit.mathew@arm.com> |
feat(sgi575): remove SGI-575 from deprecated list
As SGI-575 is not planned to be deprecated in the upcoming release cycles, remove it from the deprecated list.
Change-Id: Ic9171a3e1bec198d9305e75a
feat(sgi575): remove SGI-575 from deprecated list
As SGI-575 is not planned to be deprecated in the upcoming release cycles, remove it from the deprecated list.
Change-Id: Ic9171a3e1bec198d9305e75ac5cae4b40498537e Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
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