1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_features.h> 13 #include <arch_helpers.h> 14 #include <common/bl_common.h> 15 #include <common/debug.h> 16 #include <common/desc_image_load.h> 17 #include <drivers/generic_delay_timer.h> 18 #include <drivers/partition/partition.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/gpt_rme/gpt_rme.h> 22 #if TRANSFER_LIST 23 #include <lib/transfer_list.h> 24 #endif 25 #ifdef SPD_opteed 26 #include <lib/optee_utils.h> 27 #endif 28 #include <lib/utils.h> 29 #include <plat/arm/common/plat_arm.h> 30 #include <plat/common/platform.h> 31 32 /* Data structure which holds the extents of the trusted SRAM for BL2 */ 33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 34 35 /* Base address of fw_config received from BL1 */ 36 static uintptr_t config_base __unused; 37 38 /* 39 * Check that BL2_BASE is above ARM_FW_CONFIG_LIMIT. This reserved page is 40 * for `meminfo_t` data structure and fw_configs passed from BL1. 41 */ 42 #if TRANSFER_LIST 43 CASSERT(BL2_BASE >= PLAT_ARM_EL3_FW_HANDOFF_BASE + PLAT_ARM_FW_HANDOFF_SIZE, 44 assert_bl2_base_overflows); 45 #else 46 CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows); 47 #endif /* TRANSFER_LIST */ 48 49 /* Weak definitions may be overridden in specific ARM standard platform */ 50 #pragma weak bl2_early_platform_setup2 51 #pragma weak bl2_platform_setup 52 #pragma weak bl2_plat_arch_setup 53 #pragma weak bl2_plat_sec_mem_layout 54 55 #if ENABLE_RME 56 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 57 bl2_tzram_layout.total_base, \ 58 bl2_tzram_layout.total_size, \ 59 MT_MEMORY | MT_RW | MT_ROOT) 60 #else 61 #define MAP_BL2_TOTAL MAP_REGION_FLAT( \ 62 bl2_tzram_layout.total_base, \ 63 bl2_tzram_layout.total_size, \ 64 MT_MEMORY | MT_RW | MT_SECURE) 65 #endif /* ENABLE_RME */ 66 67 #pragma weak arm_bl2_plat_handle_post_image_load 68 69 static struct transfer_list_header *secure_tl __unused; 70 static struct transfer_list_header *ns_tl __unused; 71 72 /******************************************************************************* 73 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 74 * in x0. This memory layout is sitting at the base of the free trusted SRAM. 75 * Copy it to a safe location before its reclaimed by later BL2 functionality. 76 ******************************************************************************/ 77 void arm_bl2_early_platform_setup(uintptr_t fw_config, 78 struct meminfo *mem_layout) 79 { 80 struct transfer_list_entry *te __unused; 81 int __maybe_unused ret; 82 83 /* Initialize the console to provide early debug support */ 84 arm_console_boot_init(); 85 86 #if TRANSFER_LIST 87 // TODO: modify the prototype of this function fw_config != bl2_tl 88 secure_tl = (struct transfer_list_header *)fw_config; 89 90 te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64); 91 assert(te != NULL); 92 93 bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te); 94 transfer_list_rem(secure_tl, te); 95 #else 96 config_base = fw_config; 97 98 /* Setup the BL2 memory layout */ 99 bl2_tzram_layout = *mem_layout; 100 #endif 101 102 /* Initialise the IO layer and register platform IO devices */ 103 plat_arm_io_setup(); 104 105 /* Load partition table */ 106 #if ARM_GPT_SUPPORT 107 ret = gpt_partition_init(); 108 if (ret != 0) { 109 ERROR("GPT partition initialisation failed!\n"); 110 panic(); 111 } 112 113 #endif /* ARM_GPT_SUPPORT */ 114 } 115 116 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) 117 { 118 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); 119 120 generic_delay_timer_init(); 121 } 122 123 /* 124 * Perform BL2 preload setup. Currently we initialise the dynamic 125 * configuration here. 126 */ 127 void bl2_plat_preload_setup(void) 128 { 129 #if TRANSFER_LIST 130 arm_transfer_list_dyn_cfg_init(secure_tl); 131 #else 132 arm_bl2_dyn_cfg_init(); 133 #endif 134 135 #if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT 136 /* Always use the FIP from bank 0 */ 137 arm_set_fip_addr(0U); 138 #endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */ 139 } 140 141 /* 142 * Perform ARM standard platform setup. 143 */ 144 void arm_bl2_platform_setup(void) 145 { 146 #if !ENABLE_RME 147 /* Initialize the secure environment */ 148 plat_arm_security_setup(); 149 #endif 150 151 #if defined(PLAT_ARM_MEM_PROT_ADDR) 152 arm_nor_psci_do_static_mem_protect(); 153 #endif 154 155 #if TRANSFER_LIST 156 ns_tl = transfer_list_init((void *)FW_NS_HANDOFF_BASE, 157 PLAT_ARM_FW_HANDOFF_SIZE); 158 159 if (ns_tl == NULL) { 160 ERROR("Non-secure transfer list initialisation failed!"); 161 panic(); 162 } 163 #endif 164 } 165 166 void bl2_platform_setup(void) 167 { 168 arm_bl2_platform_setup(); 169 } 170 171 /******************************************************************************* 172 * Perform the very early platform specific architectural setup here. 173 * When RME is enabled the secure environment is initialised before 174 * initialising and enabling Granule Protection. 175 * This function initialises the MMU in a quick and dirty way. 176 ******************************************************************************/ 177 void arm_bl2_plat_arch_setup(void) 178 { 179 #if USE_COHERENT_MEM 180 /* Ensure ARM platforms don't use coherent memory in BL2. */ 181 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U); 182 #endif 183 184 const mmap_region_t bl_regions[] = { 185 MAP_BL2_TOTAL, 186 ARM_MAP_BL_RO, 187 #if USE_ROMLIB 188 ARM_MAP_ROMLIB_CODE, 189 ARM_MAP_ROMLIB_DATA, 190 #endif 191 #if !TRANSFER_LIST 192 ARM_MAP_BL_CONFIG_REGION, 193 #endif /* TRANSFER_LIST */ 194 #if ENABLE_RME 195 ARM_MAP_L0_GPT_REGION, 196 #endif 197 { 0 } 198 }; 199 200 #if ENABLE_RME 201 /* Initialise the secure environment */ 202 plat_arm_security_setup(); 203 #endif 204 setup_page_tables(bl_regions, plat_arm_get_mmap()); 205 206 #ifdef __aarch64__ 207 #if ENABLE_RME 208 /* BL2 runs in EL3 when RME enabled. */ 209 assert(get_armv9_2_feat_rme_support() != 0U); 210 enable_mmu_el3(0); 211 212 /* Initialise and enable granule protection after MMU. */ 213 arm_gpt_setup(); 214 #else 215 enable_mmu_el1(0); 216 #endif 217 #else 218 enable_mmu_svc_mon(0); 219 #endif 220 221 arm_setup_romlib(); 222 } 223 224 void bl2_plat_arch_setup(void) 225 { 226 const struct dyn_cfg_dtb_info_t *tb_fw_config_info __unused; 227 struct transfer_list_entry *te __unused; 228 arm_bl2_plat_arch_setup(); 229 230 #if TRANSFER_LIST 231 te = transfer_list_find(secure_tl, TL_TAG_TB_FW_CONFIG); 232 assert(te != NULL); 233 234 fconf_populate("TB_FW", (uintptr_t)transfer_list_entry_data(te)); 235 transfer_list_rem(secure_tl, te); 236 #else 237 /* Fill the properties struct with the info from the config dtb */ 238 fconf_populate("FW_CONFIG", config_base); 239 240 /* TB_FW_CONFIG was also loaded by BL1 */ 241 tb_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, TB_FW_CONFIG_ID); 242 assert(tb_fw_config_info != NULL); 243 244 fconf_populate("TB_FW", tb_fw_config_info->config_addr); 245 #endif 246 } 247 248 int arm_bl2_handle_post_image_load(unsigned int image_id) 249 { 250 int err = 0; 251 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 252 #ifdef SPD_opteed 253 bl_mem_params_node_t *pager_mem_params = NULL; 254 bl_mem_params_node_t *paged_mem_params = NULL; 255 #endif 256 assert(bl_mem_params != NULL); 257 258 switch (image_id) { 259 #ifdef __aarch64__ 260 case BL32_IMAGE_ID: 261 #ifdef SPD_opteed 262 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 263 assert(pager_mem_params); 264 265 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 266 assert(paged_mem_params); 267 268 err = parse_optee_header(&bl_mem_params->ep_info, 269 &pager_mem_params->image_info, 270 &paged_mem_params->image_info); 271 if (err != 0) { 272 WARN("OPTEE header parse error.\n"); 273 } 274 #endif 275 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); 276 break; 277 #endif 278 279 case BL33_IMAGE_ID: 280 /* BL33 expects to receive the primary CPU MPID (through r0) */ 281 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 282 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); 283 break; 284 285 #ifdef SCP_BL2_BASE 286 case SCP_BL2_IMAGE_ID: 287 /* The subsequent handling of SCP_BL2 is platform specific */ 288 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); 289 if (err) { 290 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 291 } 292 break; 293 #endif 294 default: 295 /* Do nothing in default case */ 296 break; 297 } 298 299 return err; 300 } 301 302 /******************************************************************************* 303 * This function can be used by the platforms to update/use image 304 * information for given `image_id`. 305 ******************************************************************************/ 306 int arm_bl2_plat_handle_post_image_load(unsigned int image_id) 307 { 308 #if defined(SPD_spmd) && BL2_ENABLE_SP_LOAD 309 /* For Secure Partitions we don't need post processing */ 310 if ((image_id >= (MAX_NUMBER_IDS - MAX_SP_IDS)) && 311 (image_id < MAX_NUMBER_IDS)) { 312 return 0; 313 } 314 #endif 315 316 #if TRANSFER_LIST 317 if (image_id == HW_CONFIG_ID) { 318 arm_transfer_list_copy_hw_config(secure_tl, ns_tl); 319 } 320 #endif /* TRANSFER_LIST */ 321 322 return arm_bl2_handle_post_image_load(image_id); 323 } 324 325 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node) 326 { 327 assert(transfer_list_set_handoff_args( 328 secure_tl, &next_param_node->ep_info) != NULL); 329 330 arm_transfer_list_populate_ep_info(next_param_node, secure_tl, ns_tl); 331 } 332