Merge "board/rddanielxlr: add support for rd-daniel config-xlr platform" into integration

spm: Normalize the style of spm core manifest

Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Change-Id: Ib39e53eb53521b8651fb30b7bf0058f7669569d5

board/rddanielxlr: add support for rd-daniel config-xlr platform

RD-Daniel Config-XLR platform has four identical chips connected via a
high speed coherent CCIX link. Each chip has four Neoverse cor

board/rddanielxlr: add support for rd-daniel config-xlr platform

RD-Daniel Config-XLR platform has four identical chips connected via a
high speed coherent CCIX link. Each chip has four Neoverse cores
connected via coherent CMN interconnect.

Change-Id: I37d1b91f2b6ba08f61c64d0288bc16a429836c08
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

show more ...

juno/sgm: Align SCP_BL2 to page boundary

This commit fixes an assertion that was triggering in certain contexts:

ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/

juno/sgm: Align SCP_BL2 to page boundary

This commit fixes an assertion that was triggering in certain contexts:

ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_core.c:790

Change-Id: Ia55b3fb4f496c8cd791ea6093d122edae0a7e92a
Signed-off-by: Chris Kay <chris.kay@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

Provide a hint to power controller for DSU cluster power down

By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an
advisory to the power controller that cluster power is not required
when all

Provide a hint to power controller for DSU cluster power down

By writing 0 to CLUSTERPWRDN DSU register bit 0, we send an
advisory to the power controller that cluster power is not required
when all cores are powered down.

The AArch32 CLUSTERPWRDN register is architecturally mapped to the
AArch64 CLUSTERPWRDN_EL1 register

Change-Id: Ie6e67c1c7d811fa25c51e2e405ca7f59bd20c81b
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

plat/arm/sgi: update mmap and xlat count

A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional

plat/arm/sgi: update mmap and xlat count

A single chip platform requires five mmap entries and a corresponding
number of translation tables. For every additional chip in the system,
three additional mmap entries are required to map the shared SRAM and
the IO regions. A corresponding number of additional translation
tables are required as well.

Change-Id: I1332a1305f2af62181387cf36954f6fb0e6f11ed
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>

show more ...

arm_fpga: Remove bogus timer initialisation

The arm_fpga platform code contains an dubious line to initialise some
timer. On closer inspection this turn out to be bogus, as this was only
needed on s

arm_fpga: Remove bogus timer initialisation

The arm_fpga platform code contains an dubious line to initialise some
timer. On closer inspection this turn out to be bogus, as this was only
needed on some special (older) FPGA board, and is actually not needed on
the current model. Also the base address was wrong anyways.

Remove the code entirely.

Change-Id: I02e71aea645051b5addb42d972d7a79f04b81106
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

show more ...

Merge "plat/arm/rddaniel: enabled GICv4 extension" into integration

plat/arm/rddaniel: enabled GICv4 extension

RD-Daniel uses GIC-Clayton as its interrupt controller which is an
implementation of GICv4.1 architecture. Hence for RD-Daniel, enable
GICv4 extension supp

plat/arm/rddaniel: enabled GICv4 extension

RD-Daniel uses GIC-Clayton as its interrupt controller which is an
implementation of GICv4.1 architecture. Hence for RD-Daniel, enable
GICv4 extension support.

Change-Id: I45ae8c82376f8fe8fc0666306822ae2db74e71b8
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

show more ...

Merge changes from topics "af/fvp_gicv4", "af/gicv4", "af/gic_extended" into integration

* changes:
FVP: Add support for GICv4 extension
TF-A: Add GICv4 extension for GIC driver
TF-A GICv3 dri

Merge changes from topics "af/fvp_gicv4", "af/gicv4", "af/gic_extended" into integration

* changes:
FVP: Add support for GICv4 extension
TF-A: Add GICv4 extension for GIC driver
TF-A GICv3 driver: Add extended PPI and SPI range

show more ...

FVP: Add support for GICv4 extension

This patch adds support for GICv4 extension for FVP platform.

Change-Id: Ia389b61266af669b1ca9b999a8b76476cab214f4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov

FVP: Add support for GICv4 extension

This patch adds support for GICv4 extension for FVP platform.

Change-Id: Ia389b61266af669b1ca9b999a8b76476cab214f4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

show more ...

Increase maximum size of BL2 image

Increased the maximum size of BL2 image in order to
accommodate the BL2 image when TF-A build with no compiler
optimization for ARM platform.

Note: As of now, "no

Increase maximum size of BL2 image

Increased the maximum size of BL2 image in order to
accommodate the BL2 image when TF-A build with no compiler
optimization for ARM platform.

Note: As of now, "no compiler optimization" build works
only when TRUSTED_BOOT_BOARD option is set to 0.

This change is verified using below CI configuration:
1. juno-no-optimize-default:juno-linux.uboot
2. fvp-no-optimize-default,fvp-default:fvp-tftf-fip.tftf-aemv8a-debug

Change-Id: I5932621237f8acd1b510682388f3ba78eae90ea4
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

Merge "arm_fpga: adapt to new way of including gicv3 files" into integration

arm_fpga: adapt to new way of including gicv3 files

with commit a6ea06f5, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fp

arm_fpga: adapt to new way of including gicv3 files

with commit a6ea06f5, the way platform includes gicv3 files has been
modified, this patch adapts to new method of including gicv3 files
for arm_fpga platform.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ic5ccae842b39b7db06d4f23c5738b174c42edf63

show more ...

Merge changes from topic "sb/fconf" into integration

* changes:
Check for out-of-bound accesses in the platform io policies
Check for out-of-bound accesses in the CoT description

Merge changes from topic "macro-cleanup" into integration

* changes:
plat: remove redundant =1 from -D option
Pass more -D options to BL*_CPPFLAGS instead of BL*_CFLAGS

Check for out-of-bound accesses in the platform io policies

The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound access

Check for out-of-bound accesses in the platform io policies

The platform io policies array is now always accessed through a fconf getter.
This gives us an ideal spot to check for out-of-bound accesses.

Remove the assertion in plat_get_image_source(), which is now redundant.

Change-Id: Iefe808d530229073b68cbd164d927b8b6662a217
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

show more ...

Fix coverity defects found on the FPGA port.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I397b642eff8a09b201f497f8d2ba39e2460c0dba

plat: remove redundant =1 from -D option

As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.

-D <name>
Predefine <name> as a macro, with definition 1.

The same appl

plat: remove redundant =1 from -D option

As GCC manual says, -D option defines a macro as 1, if =<value> is omitted.

-D <name>
Predefine <name> as a macro, with definition 1.

The same applied with Clang, too.

In the context of -D option, =1 is always redundant.

Change-Id: I487489a1ea3eb51e734741619c1e65dab1420bc4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

Merge "plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS" into integration

Merge "Create separate header for ARM specific SMCCC defines" into integration

Merge "TF-A GICv3 driver: Introduce makefile" into integration

plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS

-D is a preprocessor flag that defines a macro. So, adding it to
BL*_CPPFLAGS makes more sense. You can reference it not only from
.c files

plat: pass -D option to BL*_CPPFLAGS instead of BL*_CFLAGS

-D is a preprocessor flag that defines a macro. So, adding it to
BL*_CPPFLAGS makes more sense. You can reference it not only from
.c files but also from .S files.

Change-Id: Ib4f2f27a3ed3eae476a6a32da7ab5225ad0649de
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

show more ...

Merge "plat/sgm775: Add support for dynamic config using fconf" into integration

plat/sgm775: Add support for dynamic config using fconf

1. Necessary changes to platform makefile to include fw_config
device tree and package it in fip.bin

2. Removed hw_config node from fw_config

plat/sgm775: Add support for dynamic config using fconf

1. Necessary changes to platform makefile to include fw_config
device tree and package it in fip.bin

2. Removed hw_config node from fw_config dts as there is no
HW_CONFIG device tree source for sgm775

3. Added mbedtls_heap related properties for TBBR functionality

Change-Id: I26b940c65b17ad2fb5537141f8649785bb0fd4ad
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...