1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/interrupt_props.h> 13 #include <drivers/arm/gicv3.h> 14 #include <lib/spinlock.h> 15 16 #include "gicv3_private.h" 17 18 const gicv3_driver_data_t *gicv3_driver_data; 19 20 /* 21 * Spinlock to guard registers needing read-modify-write. APIs protected by this 22 * spinlock are used either at boot time (when only a single CPU is active), or 23 * when the system is fully coherent. 24 */ 25 static spinlock_t gic_lock; 26 27 /* 28 * Redistributor power operations are weakly bound so that they can be 29 * overridden 30 */ 31 #pragma weak gicv3_rdistif_off 32 #pragma weak gicv3_rdistif_on 33 34 /* Check interrupt ID for SGI/(E)PPI and (E)SPIs */ 35 static bool is_sgi_ppi(unsigned int id); 36 37 /* 38 * Helper macros to save and restore GICR and GICD registers 39 * corresponding to their numbers to and from the context 40 */ 41 #define RESTORE_GICR_REG(base, ctx, name, i) \ 42 gicr_write_##name((base), (i), (ctx)->gicr_##name[(i)]) 43 44 #define SAVE_GICR_REG(base, ctx, name, i) \ 45 (ctx)->gicr_##name[(i)] = gicr_read_##name((base), (i)) 46 47 /* Helper macros to save and restore GICD registers to and from the context */ 48 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 49 do { \ 50 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 51 int_id += (1U << REG##R_SHIFT)) { \ 52 gicd_write_##reg((base), int_id, \ 53 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 54 REG##R_SHIFT]); \ 55 } \ 56 } while (false) 57 58 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ 59 do { \ 60 for (unsigned int int_id = MIN_SPI_ID; int_id < (intr_num);\ 61 int_id += (1U << REG##R_SHIFT)) { \ 62 (ctx)->gicd_##reg[(int_id - MIN_SPI_ID) >> \ 63 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \ 64 } \ 65 } while (false) 66 67 #if GIC_EXT_INTID 68 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 69 do { \ 70 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 71 int_id += (1U << REG##R_SHIFT)) { \ 72 gicd_write_##reg((base), int_id, \ 73 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\ 74 >> REG##R_SHIFT]); \ 75 } \ 76 } while (false) 77 78 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ 79 do { \ 80 for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\ 81 int_id += (1U << REG##R_SHIFT)) { \ 82 (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\ 83 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\ 84 } \ 85 } while (false) 86 #else 87 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) 88 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) 89 #endif /* GIC_EXT_INTID */ 90 91 /******************************************************************************* 92 * This function initialises the ARM GICv3 driver in EL3 with provided platform 93 * inputs. 94 ******************************************************************************/ 95 void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) 96 { 97 unsigned int gic_version; 98 unsigned int gicv2_compat; 99 100 assert(plat_driver_data != NULL); 101 assert(plat_driver_data->gicd_base != 0U); 102 assert(plat_driver_data->rdistif_num != 0U); 103 assert(plat_driver_data->rdistif_base_addrs != NULL); 104 105 assert(IS_IN_EL3()); 106 107 assert((plat_driver_data->interrupt_props_num != 0U) ? 108 (plat_driver_data->interrupt_props != NULL) : 1); 109 110 /* Check for system register support */ 111 #ifndef __aarch64__ 112 assert((read_id_pfr1() & 113 (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U); 114 #else 115 assert((read_id_aa64pfr0_el1() & 116 (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U); 117 #endif /* !__aarch64__ */ 118 119 gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); 120 gic_version >>= PIDR2_ARCH_REV_SHIFT; 121 gic_version &= PIDR2_ARCH_REV_MASK; 122 123 /* Check GIC version */ 124 #if GIC_ENABLE_V4_EXTN 125 assert(gic_version == ARCH_REV_GICV4); 126 127 /* GICv4 supports Direct Virtual LPI injection */ 128 assert((gicd_read_typer(plat_driver_data->gicd_base) 129 & TYPER_DVIS) != 0); 130 #else 131 assert(gic_version == ARCH_REV_GICV3); 132 #endif 133 /* 134 * Find out whether the GIC supports the GICv2 compatibility mode. 135 * The ARE_S bit resets to 0 if supported 136 */ 137 gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); 138 gicv2_compat >>= CTLR_ARE_S_SHIFT; 139 gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK; 140 141 if (plat_driver_data->gicr_base != 0U) { 142 /* 143 * Find the base address of each implemented Redistributor interface. 144 * The number of interfaces should be equal to the number of CPUs in the 145 * system. The memory for saving these addresses has to be allocated by 146 * the platform port 147 */ 148 gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, 149 plat_driver_data->rdistif_num, 150 plat_driver_data->gicr_base, 151 plat_driver_data->mpidr_to_core_pos); 152 #if !HW_ASSISTED_COHERENCY 153 /* 154 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 155 */ 156 flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs), 157 plat_driver_data->rdistif_num * 158 sizeof(*(plat_driver_data->rdistif_base_addrs))); 159 #endif 160 } 161 gicv3_driver_data = plat_driver_data; 162 163 /* 164 * The GIC driver data is initialized by the primary CPU with caches 165 * enabled. When the secondary CPU boots up, it initializes the 166 * GICC/GICR interface with the caches disabled. Hence flush the 167 * driver data to ensure coherency. This is not required if the 168 * platform has HW_ASSISTED_COHERENCY enabled. 169 */ 170 #if !HW_ASSISTED_COHERENCY 171 flush_dcache_range((uintptr_t)&gicv3_driver_data, 172 sizeof(gicv3_driver_data)); 173 flush_dcache_range((uintptr_t)gicv3_driver_data, 174 sizeof(*gicv3_driver_data)); 175 #endif 176 INFO("GICv%u with%s legacy support detected.\n", gic_version, 177 (gicv2_compat == 0U) ? "" : "out"); 178 INFO("ARM GICv%u driver initialized in EL3\n", gic_version); 179 } 180 181 /******************************************************************************* 182 * This function initialises the GIC distributor interface based upon the data 183 * provided by the platform while initialising the driver. 184 ******************************************************************************/ 185 void __init gicv3_distif_init(void) 186 { 187 unsigned int bitmap; 188 189 assert(gicv3_driver_data != NULL); 190 assert(gicv3_driver_data->gicd_base != 0U); 191 192 assert(IS_IN_EL3()); 193 194 /* 195 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 196 * the ARE_S bit. The Distributor might generate a system error 197 * otherwise. 198 */ 199 gicd_clr_ctlr(gicv3_driver_data->gicd_base, 200 CTLR_ENABLE_G0_BIT | 201 CTLR_ENABLE_G1S_BIT | 202 CTLR_ENABLE_G1NS_BIT, 203 RWP_TRUE); 204 205 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 206 gicd_set_ctlr(gicv3_driver_data->gicd_base, 207 CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 208 209 /* Set the default attribute of all (E)SPIs */ 210 gicv3_spis_config_defaults(gicv3_driver_data->gicd_base); 211 212 bitmap = gicv3_secure_spis_config_props( 213 gicv3_driver_data->gicd_base, 214 gicv3_driver_data->interrupt_props, 215 gicv3_driver_data->interrupt_props_num); 216 217 /* Enable the secure (E)SPIs now that they have been configured */ 218 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 219 } 220 221 /******************************************************************************* 222 * This function initialises the GIC Redistributor interface of the calling CPU 223 * (identified by the 'proc_num' parameter) based upon the data provided by the 224 * platform while initialising the driver. 225 ******************************************************************************/ 226 void gicv3_rdistif_init(unsigned int proc_num) 227 { 228 uintptr_t gicr_base; 229 unsigned int bitmap; 230 uint32_t ctlr; 231 232 assert(gicv3_driver_data != NULL); 233 assert(proc_num < gicv3_driver_data->rdistif_num); 234 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 235 assert(gicv3_driver_data->gicd_base != 0U); 236 237 ctlr = gicd_read_ctlr(gicv3_driver_data->gicd_base); 238 assert((ctlr & CTLR_ARE_S_BIT) != 0U); 239 240 assert(IS_IN_EL3()); 241 242 /* Power on redistributor */ 243 gicv3_rdistif_on(proc_num); 244 245 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 246 assert(gicr_base != 0U); 247 248 /* Set the default attribute of all SGIs and (E)PPIs */ 249 gicv3_ppi_sgi_config_defaults(gicr_base); 250 251 bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base, 252 gicv3_driver_data->interrupt_props, 253 gicv3_driver_data->interrupt_props_num); 254 255 /* Enable interrupt groups as required, if not already */ 256 if ((ctlr & bitmap) != bitmap) { 257 gicd_set_ctlr(gicv3_driver_data->gicd_base, bitmap, RWP_TRUE); 258 } 259 } 260 261 /******************************************************************************* 262 * Functions to perform power operations on GIC Redistributor 263 ******************************************************************************/ 264 void gicv3_rdistif_off(unsigned int proc_num) 265 { 266 } 267 268 void gicv3_rdistif_on(unsigned int proc_num) 269 { 270 } 271 272 /******************************************************************************* 273 * This function enables the GIC CPU interface of the calling CPU using only 274 * system register accesses. 275 ******************************************************************************/ 276 void gicv3_cpuif_enable(unsigned int proc_num) 277 { 278 uintptr_t gicr_base; 279 u_register_t scr_el3; 280 unsigned int icc_sre_el3; 281 282 assert(gicv3_driver_data != NULL); 283 assert(proc_num < gicv3_driver_data->rdistif_num); 284 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 285 assert(IS_IN_EL3()); 286 287 /* Mark the connected core as awake */ 288 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 289 gicv3_rdistif_mark_core_awake(gicr_base); 290 291 /* Disable the legacy interrupt bypass */ 292 icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; 293 294 /* 295 * Enable system register access for EL3 and allow lower exception 296 * levels to configure the same for themselves. If the legacy mode is 297 * not supported, the SRE bit is RAO/WI 298 */ 299 icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); 300 write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); 301 302 scr_el3 = read_scr_el3(); 303 304 /* 305 * Switch to NS state to write Non secure ICC_SRE_EL1 and 306 * ICC_SRE_EL2 registers. 307 */ 308 write_scr_el3(scr_el3 | SCR_NS_BIT); 309 isb(); 310 311 write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); 312 write_icc_sre_el1(ICC_SRE_SRE_BIT); 313 isb(); 314 315 /* Switch to secure state. */ 316 write_scr_el3(scr_el3 & (~SCR_NS_BIT)); 317 isb(); 318 319 /* Write the secure ICC_SRE_EL1 register */ 320 write_icc_sre_el1(ICC_SRE_SRE_BIT); 321 isb(); 322 323 /* Program the idle priority in the PMR */ 324 write_icc_pmr_el1(GIC_PRI_MASK); 325 326 /* Enable Group0 interrupts */ 327 write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); 328 329 /* Enable Group1 Secure interrupts */ 330 write_icc_igrpen1_el3(read_icc_igrpen1_el3() | 331 IGRPEN1_EL3_ENABLE_G1S_BIT); 332 isb(); 333 } 334 335 /******************************************************************************* 336 * This function disables the GIC CPU interface of the calling CPU using 337 * only system register accesses. 338 ******************************************************************************/ 339 void gicv3_cpuif_disable(unsigned int proc_num) 340 { 341 uintptr_t gicr_base; 342 343 assert(gicv3_driver_data != NULL); 344 assert(proc_num < gicv3_driver_data->rdistif_num); 345 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 346 347 assert(IS_IN_EL3()); 348 349 /* Disable legacy interrupt bypass */ 350 write_icc_sre_el3(read_icc_sre_el3() | 351 (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); 352 353 /* Disable Group0 interrupts */ 354 write_icc_igrpen0_el1(read_icc_igrpen0_el1() & 355 ~IGRPEN1_EL1_ENABLE_G0_BIT); 356 357 /* Disable Group1 Secure and Non-Secure interrupts */ 358 write_icc_igrpen1_el3(read_icc_igrpen1_el3() & 359 ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | 360 IGRPEN1_EL3_ENABLE_G1S_BIT)); 361 362 /* Synchronise accesses to group enable registers */ 363 isb(); 364 365 /* Mark the connected core as asleep */ 366 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 367 assert(gicr_base != 0U); 368 gicv3_rdistif_mark_core_asleep(gicr_base); 369 } 370 371 /******************************************************************************* 372 * This function returns the id of the highest priority pending interrupt at 373 * the GIC cpu interface. 374 ******************************************************************************/ 375 unsigned int gicv3_get_pending_interrupt_id(void) 376 { 377 unsigned int id; 378 379 assert(IS_IN_EL3()); 380 id = (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 381 382 /* 383 * If the ID is special identifier corresponding to G1S or G1NS 384 * interrupt, then read the highest pending group 1 interrupt. 385 */ 386 if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) { 387 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; 388 } 389 390 return id; 391 } 392 393 /******************************************************************************* 394 * This function returns the type of the highest priority pending interrupt at 395 * the GIC cpu interface. The return values can be one of the following : 396 * PENDING_G1S_INTID : The interrupt type is secure Group 1. 397 * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. 398 * 0 - 1019 : The interrupt type is secure Group 0. 399 * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with 400 * sufficient priority to be signaled 401 ******************************************************************************/ 402 unsigned int gicv3_get_pending_interrupt_type(void) 403 { 404 assert(IS_IN_EL3()); 405 return (uint32_t)read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; 406 } 407 408 /******************************************************************************* 409 * This function returns the type of the interrupt id depending upon the group 410 * this interrupt has been configured under by the interrupt controller i.e. 411 * group0 or group1 Secure / Non Secure. The return value can be one of the 412 * following : 413 * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt 414 * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt 415 * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure 416 * interrupt. 417 ******************************************************************************/ 418 unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int proc_num) 419 { 420 unsigned int igroup, grpmodr; 421 uintptr_t gicr_base; 422 423 assert(IS_IN_EL3()); 424 assert(gicv3_driver_data != NULL); 425 426 /* Ensure the parameters are valid */ 427 assert((id < PENDING_G1S_INTID) || (id >= MIN_LPI_ID)); 428 assert(proc_num < gicv3_driver_data->rdistif_num); 429 430 /* All LPI interrupts are Group 1 non secure */ 431 if (id >= MIN_LPI_ID) { 432 return INTR_GROUP1NS; 433 } 434 435 /* Check interrupt ID */ 436 if (is_sgi_ppi(id)) { 437 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 438 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 439 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 440 igroup = gicr_get_igroupr(gicr_base, id); 441 grpmodr = gicr_get_igrpmodr(gicr_base, id); 442 } else { 443 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 444 assert(gicv3_driver_data->gicd_base != 0U); 445 igroup = gicd_get_igroupr(gicv3_driver_data->gicd_base, id); 446 grpmodr = gicd_get_igrpmodr(gicv3_driver_data->gicd_base, id); 447 } 448 449 /* 450 * If the IGROUP bit is set, then it is a Group 1 Non secure 451 * interrupt 452 */ 453 if (igroup != 0U) { 454 return INTR_GROUP1NS; 455 } 456 457 /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ 458 if (grpmodr != 0U) { 459 return INTR_GROUP1S; 460 } 461 462 /* Else it is a Group 0 Secure interrupt */ 463 return INTR_GROUP0; 464 } 465 466 /***************************************************************************** 467 * Function to save and disable the GIC ITS register context. The power 468 * management of GIC ITS is implementation-defined and this function doesn't 469 * save any memory structures required to support ITS. As the sequence to save 470 * this state is implementation defined, it should be executed in platform 471 * specific code. Calling this function alone and then powering down the GIC and 472 * ITS without implementing the aforementioned platform specific code will 473 * corrupt the ITS state. 474 * 475 * This function must be invoked after the GIC CPU interface is disabled. 476 *****************************************************************************/ 477 void gicv3_its_save_disable(uintptr_t gits_base, 478 gicv3_its_ctx_t * const its_ctx) 479 { 480 unsigned int i; 481 482 assert(gicv3_driver_data != NULL); 483 assert(IS_IN_EL3()); 484 assert(its_ctx != NULL); 485 assert(gits_base != 0U); 486 487 its_ctx->gits_ctlr = gits_read_ctlr(gits_base); 488 489 /* Disable the ITS */ 490 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 491 492 /* Wait for quiescent state */ 493 gits_wait_for_quiescent_bit(gits_base); 494 495 its_ctx->gits_cbaser = gits_read_cbaser(gits_base); 496 its_ctx->gits_cwriter = gits_read_cwriter(gits_base); 497 498 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 499 its_ctx->gits_baser[i] = gits_read_baser(gits_base, i); 500 } 501 } 502 503 /***************************************************************************** 504 * Function to restore the GIC ITS register context. The power 505 * management of GIC ITS is implementation defined and this function doesn't 506 * restore any memory structures required to support ITS. The assumption is 507 * that these structures are in memory and are retained during system suspend. 508 * 509 * This must be invoked before the GIC CPU interface is enabled. 510 *****************************************************************************/ 511 void gicv3_its_restore(uintptr_t gits_base, 512 const gicv3_its_ctx_t * const its_ctx) 513 { 514 unsigned int i; 515 516 assert(gicv3_driver_data != NULL); 517 assert(IS_IN_EL3()); 518 assert(its_ctx != NULL); 519 assert(gits_base != 0U); 520 521 /* Assert that the GITS is disabled and quiescent */ 522 assert((gits_read_ctlr(gits_base) & GITS_CTLR_ENABLED_BIT) == 0U); 523 assert((gits_read_ctlr(gits_base) & GITS_CTLR_QUIESCENT_BIT) != 0U); 524 525 gits_write_cbaser(gits_base, its_ctx->gits_cbaser); 526 gits_write_cwriter(gits_base, its_ctx->gits_cwriter); 527 528 for (i = 0U; i < ARRAY_SIZE(its_ctx->gits_baser); i++) { 529 gits_write_baser(gits_base, i, its_ctx->gits_baser[i]); 530 } 531 532 /* Restore the ITS CTLR but leave the ITS disabled */ 533 gits_write_ctlr(gits_base, its_ctx->gits_ctlr & ~GITS_CTLR_ENABLED_BIT); 534 } 535 536 /***************************************************************************** 537 * Function to save the GIC Redistributor register context. This function 538 * must be invoked after CPU interface disable and prior to Distributor save. 539 *****************************************************************************/ 540 void gicv3_rdistif_save(unsigned int proc_num, 541 gicv3_redist_ctx_t * const rdist_ctx) 542 { 543 uintptr_t gicr_base; 544 unsigned int i, ppi_regs_num, regs_num; 545 546 assert(gicv3_driver_data != NULL); 547 assert(proc_num < gicv3_driver_data->rdistif_num); 548 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 549 assert(IS_IN_EL3()); 550 assert(rdist_ctx != NULL); 551 552 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 553 554 #if GIC_EXT_INTID 555 /* Calculate number of PPI registers */ 556 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 557 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 558 /* All other values except PPInum [0-2] are reserved */ 559 if (ppi_regs_num > 3U) { 560 ppi_regs_num = 1U; 561 } 562 #else 563 ppi_regs_num = 1U; 564 #endif 565 /* 566 * Wait for any write to GICR_CTLR to complete before trying to save any 567 * state. 568 */ 569 gicr_wait_for_pending_write(gicr_base); 570 571 rdist_ctx->gicr_ctlr = gicr_read_ctlr(gicr_base); 572 573 rdist_ctx->gicr_propbaser = gicr_read_propbaser(gicr_base); 574 rdist_ctx->gicr_pendbaser = gicr_read_pendbaser(gicr_base); 575 576 /* 32 interrupt IDs per register */ 577 for (i = 0U; i < ppi_regs_num; ++i) { 578 SAVE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 579 SAVE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 580 SAVE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 581 SAVE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 582 SAVE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 583 } 584 585 /* 16 interrupt IDs per GICR_ICFGR register */ 586 regs_num = ppi_regs_num << 1; 587 for (i = 0U; i < regs_num; ++i) { 588 SAVE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 589 } 590 591 rdist_ctx->gicr_nsacr = gicr_read_nsacr(gicr_base); 592 593 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 594 regs_num = ppi_regs_num << 3; 595 for (i = 0U; i < regs_num; ++i) { 596 SAVE_GICR_REG(gicr_base, rdist_ctx, ipriorityr, i); 597 } 598 599 /* 600 * Call the pre-save hook that implements the IMP DEF sequence that may 601 * be required on some GIC implementations. As this may need to access 602 * the Redistributor registers, we pass it proc_num. 603 */ 604 gicv3_distif_pre_save(proc_num); 605 } 606 607 /***************************************************************************** 608 * Function to restore the GIC Redistributor register context. We disable 609 * LPI and per-cpu interrupts before we start restore of the Redistributor. 610 * This function must be invoked after Distributor restore but prior to 611 * CPU interface enable. The pending and active interrupts are restored 612 * after the interrupts are fully configured and enabled. 613 *****************************************************************************/ 614 void gicv3_rdistif_init_restore(unsigned int proc_num, 615 const gicv3_redist_ctx_t * const rdist_ctx) 616 { 617 uintptr_t gicr_base; 618 unsigned int i, ppi_regs_num, regs_num; 619 620 assert(gicv3_driver_data != NULL); 621 assert(proc_num < gicv3_driver_data->rdistif_num); 622 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 623 assert(IS_IN_EL3()); 624 assert(rdist_ctx != NULL); 625 626 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 627 628 #if GIC_EXT_INTID 629 /* Calculate number of PPI registers */ 630 ppi_regs_num = (unsigned int)((gicr_read_typer(gicr_base) >> 631 TYPER_PPI_NUM_SHIFT) & TYPER_PPI_NUM_MASK) + 1; 632 /* All other values except PPInum [0-2] are reserved */ 633 if (ppi_regs_num > 3U) { 634 ppi_regs_num = 1U; 635 } 636 #else 637 ppi_regs_num = 1U; 638 #endif 639 /* Power on redistributor */ 640 gicv3_rdistif_on(proc_num); 641 642 /* 643 * Call the post-restore hook that implements the IMP DEF sequence that 644 * may be required on some GIC implementations. As this may need to 645 * access the Redistributor registers, we pass it proc_num. 646 */ 647 gicv3_distif_post_restore(proc_num); 648 649 /* 650 * Disable all SGIs (imp. def.)/(E)PPIs before configuring them. 651 * This is a more scalable approach as it avoids clearing the enable 652 * bits in the GICD_CTLR. 653 */ 654 for (i = 0U; i < ppi_regs_num; ++i) { 655 gicr_write_icenabler(gicr_base, i, ~0U); 656 } 657 658 /* Wait for pending writes to GICR_ICENABLER */ 659 gicr_wait_for_pending_write(gicr_base); 660 661 /* 662 * Disable the LPIs to avoid unpredictable behavior when writing to 663 * GICR_PROPBASER and GICR_PENDBASER. 664 */ 665 gicr_write_ctlr(gicr_base, 666 rdist_ctx->gicr_ctlr & ~(GICR_CTLR_EN_LPIS_BIT)); 667 668 /* Restore registers' content */ 669 gicr_write_propbaser(gicr_base, rdist_ctx->gicr_propbaser); 670 gicr_write_pendbaser(gicr_base, rdist_ctx->gicr_pendbaser); 671 672 /* 32 interrupt IDs per register */ 673 for (i = 0U; i < ppi_regs_num; ++i) { 674 RESTORE_GICR_REG(gicr_base, rdist_ctx, igroupr, i); 675 RESTORE_GICR_REG(gicr_base, rdist_ctx, igrpmodr, i); 676 } 677 678 /* 4 interrupt IDs per GICR_IPRIORITYR register */ 679 regs_num = ppi_regs_num << 3; 680 for (i = 0U; i < regs_num; ++i) { 681 RESTORE_GICR_REG(gicr_base, rdist_ctx, ipriorityr, i); 682 } 683 684 /* 16 interrupt IDs per GICR_ICFGR register */ 685 regs_num = ppi_regs_num << 1; 686 for (i = 0U; i < regs_num; ++i) { 687 RESTORE_GICR_REG(gicr_base, rdist_ctx, icfgr, i); 688 } 689 690 gicr_write_nsacr(gicr_base, rdist_ctx->gicr_nsacr); 691 692 /* Restore after group and priorities are set. 693 * 32 interrupt IDs per register 694 */ 695 for (i = 0U; i < ppi_regs_num; ++i) { 696 RESTORE_GICR_REG(gicr_base, rdist_ctx, ispendr, i); 697 RESTORE_GICR_REG(gicr_base, rdist_ctx, isactiver, i); 698 } 699 700 /* 701 * Wait for all writes to the Distributor to complete before enabling 702 * the SGI and (E)PPIs. 703 */ 704 gicr_wait_for_upstream_pending_write(gicr_base); 705 706 /* 32 interrupt IDs per GICR_ISENABLER register */ 707 for (i = 0U; i < ppi_regs_num; ++i) { 708 RESTORE_GICR_REG(gicr_base, rdist_ctx, isenabler, i); 709 } 710 711 /* 712 * Restore GICR_CTLR.Enable_LPIs bit and wait for pending writes in case 713 * the first write to GICR_CTLR was still in flight (this write only 714 * restores GICR_CTLR.Enable_LPIs and no waiting is required for this 715 * bit). 716 */ 717 gicr_write_ctlr(gicr_base, rdist_ctx->gicr_ctlr); 718 gicr_wait_for_pending_write(gicr_base); 719 } 720 721 /***************************************************************************** 722 * Function to save the GIC Distributor register context. This function 723 * must be invoked after CPU interface disable and Redistributor save. 724 *****************************************************************************/ 725 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx) 726 { 727 unsigned int typer_reg, num_ints; 728 #if GIC_EXT_INTID 729 unsigned int num_eints; 730 #endif 731 732 assert(gicv3_driver_data != NULL); 733 assert(gicv3_driver_data->gicd_base != 0U); 734 assert(IS_IN_EL3()); 735 assert(dist_ctx != NULL); 736 737 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 738 739 typer_reg = gicd_read_typer(gicd_base); 740 741 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 742 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 743 744 /* Filter out special INTIDs 1020-1023 */ 745 if (num_ints > (MAX_SPI_ID + 1U)) { 746 num_ints = MAX_SPI_ID + 1U; 747 } 748 749 #if GIC_EXT_INTID 750 /* Check if extended SPI range is implemented */ 751 if ((typer_reg & TYPER_ESPI) != 0U) { 752 /* 753 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 754 */ 755 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 756 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1; 757 } else { 758 num_eints = 0U; 759 } 760 #endif 761 /* Wait for pending write to complete */ 762 gicd_wait_for_pending_write(gicd_base); 763 764 /* Save the GICD_CTLR */ 765 dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base); 766 767 /* Save GICD_IGROUPR for INTIDs 32 - 1019 */ 768 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 769 770 /* Save GICD_IGROUPRE for INTIDs 4096 - 5119 */ 771 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 772 773 /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */ 774 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 775 776 /* Save GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 777 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 778 779 /* Save GICD_ISPENDR for INTIDs 32 - 1019 */ 780 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 781 782 /* Save GICD_ISPENDRE for INTIDs 4096 - 5119 */ 783 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 784 785 /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */ 786 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 787 788 /* Save GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 789 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 790 791 /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */ 792 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 793 794 /* Save GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 795 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 796 797 /* Save GICD_ICFGR for INTIDs 32 - 1019 */ 798 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 799 800 /* Save GICD_ICFGRE for INTIDs 4096 - 5119 */ 801 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 802 803 /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */ 804 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 805 806 /* Save GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 807 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 808 809 /* Save GICD_NSACR for INTIDs 32 - 1019 */ 810 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 811 812 /* Save GICD_NSACRE for INTIDs 4096 - 5119 */ 813 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 814 815 /* Save GICD_IROUTER for INTIDs 32 - 1019 */ 816 SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 817 818 /* Save GICD_IROUTERE for INTIDs 4096 - 5119 */ 819 SAVE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 820 821 /* 822 * GICD_ITARGETSR<n> and GICD_SPENDSGIR<n> are RAZ/WI when 823 * GICD_CTLR.ARE_(S|NS) bits are set which is the case for our GICv3 824 * driver. 825 */ 826 } 827 828 /***************************************************************************** 829 * Function to restore the GIC Distributor register context. We disable G0, G1S 830 * and G1NS interrupt groups before we start restore of the Distributor. This 831 * function must be invoked prior to Redistributor restore and CPU interface 832 * enable. The pending and active interrupts are restored after the interrupts 833 * are fully configured and enabled. 834 *****************************************************************************/ 835 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx) 836 { 837 unsigned int typer_reg, num_ints; 838 #if GIC_EXT_INTID 839 unsigned int num_eints; 840 #endif 841 842 assert(gicv3_driver_data != NULL); 843 assert(gicv3_driver_data->gicd_base != 0U); 844 assert(IS_IN_EL3()); 845 assert(dist_ctx != NULL); 846 847 uintptr_t gicd_base = gicv3_driver_data->gicd_base; 848 849 /* 850 * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring 851 * the ARE_S bit. The Distributor might generate a system error 852 * otherwise. 853 */ 854 gicd_clr_ctlr(gicd_base, 855 CTLR_ENABLE_G0_BIT | 856 CTLR_ENABLE_G1S_BIT | 857 CTLR_ENABLE_G1NS_BIT, 858 RWP_TRUE); 859 860 /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ 861 gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); 862 863 typer_reg = gicd_read_typer(gicd_base); 864 865 /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */ 866 num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5; 867 868 /* Filter out special INTIDs 1020-1023 */ 869 if (num_ints > (MAX_SPI_ID + 1U)) { 870 num_ints = MAX_SPI_ID + 1U; 871 } 872 873 #if GIC_EXT_INTID 874 /* Check if extended SPI range is implemented */ 875 if ((typer_reg & TYPER_ESPI) != 0U) { 876 /* 877 * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095 878 */ 879 num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) & 880 TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1; 881 } else { 882 num_eints = 0U; 883 } 884 #endif 885 /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */ 886 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP); 887 888 /* Restore GICD_IGROUPRE for INTIDs 4096 - 5119 */ 889 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igroupr, IGROUP); 890 891 /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */ 892 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITY); 893 894 /* Restore GICD_IPRIORITYRE for INTIDs 4096 - 5119 */ 895 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ipriorityr, IPRIORITY); 896 897 /* Restore GICD_ICFGR for INTIDs 32 - 1019 */ 898 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFG); 899 900 /* Restore GICD_ICFGRE for INTIDs 4096 - 5119 */ 901 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, icfgr, ICFG); 902 903 /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */ 904 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMOD); 905 906 /* Restore GICD_IGRPMODRE for INTIDs 4096 - 5119 */ 907 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, igrpmodr, IGRPMOD); 908 909 /* Restore GICD_NSACR for INTIDs 32 - 1019 */ 910 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSAC); 911 912 /* Restore GICD_NSACRE for INTIDs 4096 - 5119 */ 913 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, nsacr, NSAC); 914 915 /* Restore GICD_IROUTER for INTIDs 32 - 1019 */ 916 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTE); 917 918 /* Restore GICD_IROUTERE for INTIDs 4096 - 5119 */ 919 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, irouter, IROUTE); 920 921 /* 922 * Restore ISENABLER(E), ISPENDR(E) and ISACTIVER(E) after 923 * the interrupts are configured. 924 */ 925 926 /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */ 927 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLE); 928 929 /* Restore GICD_ISENABLERE for INT_IDs 4096 - 5119 */ 930 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isenabler, ISENABLE); 931 932 /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */ 933 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPEND); 934 935 /* Restore GICD_ISPENDRE for INTIDs 4096 - 5119 */ 936 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, ispendr, ISPEND); 937 938 /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */ 939 RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVE); 940 941 /* Restore GICD_ISACTIVERE for INTIDs 4096 - 5119 */ 942 RESTORE_GICD_EREGS(gicd_base, dist_ctx, num_eints, isactiver, ISACTIVE); 943 944 /* Restore the GICD_CTLR */ 945 gicd_write_ctlr(gicd_base, dist_ctx->gicd_ctlr); 946 gicd_wait_for_pending_write(gicd_base); 947 } 948 949 /******************************************************************************* 950 * This function gets the priority of the interrupt the processor is currently 951 * servicing. 952 ******************************************************************************/ 953 unsigned int gicv3_get_running_priority(void) 954 { 955 return (unsigned int)read_icc_rpr_el1(); 956 } 957 958 /******************************************************************************* 959 * This function checks if the interrupt identified by id is active (whether the 960 * state is either active, or active and pending). The proc_num is used if the 961 * interrupt is SGI or (E)PPI and programs the corresponding Redistributor 962 * interface. 963 ******************************************************************************/ 964 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num) 965 { 966 assert(gicv3_driver_data != NULL); 967 assert(gicv3_driver_data->gicd_base != 0U); 968 assert(proc_num < gicv3_driver_data->rdistif_num); 969 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 970 971 /* Check interrupt ID */ 972 if (is_sgi_ppi(id)) { 973 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 974 return gicr_get_isactiver( 975 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 976 } 977 978 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 979 return gicd_get_isactiver(gicv3_driver_data->gicd_base, id); 980 } 981 982 /******************************************************************************* 983 * This function enables the interrupt identified by id. The proc_num 984 * is used if the interrupt is SGI or PPI, and programs the corresponding 985 * Redistributor interface. 986 ******************************************************************************/ 987 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num) 988 { 989 assert(gicv3_driver_data != NULL); 990 assert(gicv3_driver_data->gicd_base != 0U); 991 assert(proc_num < gicv3_driver_data->rdistif_num); 992 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 993 994 /* 995 * Ensure that any shared variable updates depending on out of band 996 * interrupt trigger are observed before enabling interrupt. 997 */ 998 dsbishst(); 999 1000 /* Check interrupt ID */ 1001 if (is_sgi_ppi(id)) { 1002 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1003 gicr_set_isenabler( 1004 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1005 } else { 1006 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1007 gicd_set_isenabler(gicv3_driver_data->gicd_base, id); 1008 } 1009 } 1010 1011 /******************************************************************************* 1012 * This function disables the interrupt identified by id. The proc_num 1013 * is used if the interrupt is SGI or PPI, and programs the corresponding 1014 * Redistributor interface. 1015 ******************************************************************************/ 1016 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num) 1017 { 1018 assert(gicv3_driver_data != NULL); 1019 assert(gicv3_driver_data->gicd_base != 0U); 1020 assert(proc_num < gicv3_driver_data->rdistif_num); 1021 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1022 1023 /* 1024 * Disable interrupt, and ensure that any shared variable updates 1025 * depending on out of band interrupt trigger are observed afterwards. 1026 */ 1027 1028 /* Check interrupt ID */ 1029 if (is_sgi_ppi(id)) { 1030 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1031 gicr_set_icenabler( 1032 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1033 1034 /* Write to clear enable requires waiting for pending writes */ 1035 gicr_wait_for_pending_write( 1036 gicv3_driver_data->rdistif_base_addrs[proc_num]); 1037 } else { 1038 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1039 gicd_set_icenabler(gicv3_driver_data->gicd_base, id); 1040 1041 /* Write to clear enable requires waiting for pending writes */ 1042 gicd_wait_for_pending_write(gicv3_driver_data->gicd_base); 1043 } 1044 1045 dsbishst(); 1046 } 1047 1048 /******************************************************************************* 1049 * This function sets the interrupt priority as supplied for the given interrupt 1050 * id. 1051 ******************************************************************************/ 1052 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num, 1053 unsigned int priority) 1054 { 1055 uintptr_t gicr_base; 1056 1057 assert(gicv3_driver_data != NULL); 1058 assert(gicv3_driver_data->gicd_base != 0U); 1059 assert(proc_num < gicv3_driver_data->rdistif_num); 1060 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1061 1062 /* Check interrupt ID */ 1063 if (is_sgi_ppi(id)) { 1064 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1065 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1066 gicr_set_ipriorityr(gicr_base, id, priority); 1067 } else { 1068 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1069 gicd_set_ipriorityr(gicv3_driver_data->gicd_base, id, priority); 1070 } 1071 } 1072 1073 /******************************************************************************* 1074 * This function assigns group for the interrupt identified by id. The proc_num 1075 * is used if the interrupt is SGI or (E)PPI, and programs the corresponding 1076 * Redistributor interface. The group can be any of GICV3_INTR_GROUP* 1077 ******************************************************************************/ 1078 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num, 1079 unsigned int type) 1080 { 1081 bool igroup = false, grpmod = false; 1082 uintptr_t gicr_base; 1083 1084 assert(gicv3_driver_data != NULL); 1085 assert(gicv3_driver_data->gicd_base != 0U); 1086 assert(proc_num < gicv3_driver_data->rdistif_num); 1087 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1088 1089 switch (type) { 1090 case INTR_GROUP1S: 1091 igroup = false; 1092 grpmod = true; 1093 break; 1094 case INTR_GROUP0: 1095 igroup = false; 1096 grpmod = false; 1097 break; 1098 case INTR_GROUP1NS: 1099 igroup = true; 1100 grpmod = false; 1101 break; 1102 default: 1103 assert(false); 1104 break; 1105 } 1106 1107 /* Check interrupt ID */ 1108 if (is_sgi_ppi(id)) { 1109 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1110 gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num]; 1111 1112 igroup ? gicr_set_igroupr(gicr_base, id) : 1113 gicr_clr_igroupr(gicr_base, id); 1114 grpmod ? gicr_set_igrpmodr(gicr_base, id) : 1115 gicr_clr_igrpmodr(gicr_base, id); 1116 } else { 1117 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1118 1119 /* Serialize read-modify-write to Distributor registers */ 1120 spin_lock(&gic_lock); 1121 1122 igroup ? gicd_set_igroupr(gicv3_driver_data->gicd_base, id) : 1123 gicd_clr_igroupr(gicv3_driver_data->gicd_base, id); 1124 grpmod ? gicd_set_igrpmodr(gicv3_driver_data->gicd_base, id) : 1125 gicd_clr_igrpmodr(gicv3_driver_data->gicd_base, id); 1126 1127 spin_unlock(&gic_lock); 1128 } 1129 } 1130 1131 /******************************************************************************* 1132 * This function raises the specified Secure Group 0 SGI. 1133 * 1134 * The target parameter must be a valid MPIDR in the system. 1135 ******************************************************************************/ 1136 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target) 1137 { 1138 unsigned int tgt, aff3, aff2, aff1, aff0; 1139 uint64_t sgi_val; 1140 1141 /* Verify interrupt number is in the SGI range */ 1142 assert((sgi_num >= MIN_SGI_ID) && (sgi_num < MIN_PPI_ID)); 1143 1144 /* Extract affinity fields from target */ 1145 aff0 = MPIDR_AFFLVL0_VAL(target); 1146 aff1 = MPIDR_AFFLVL1_VAL(target); 1147 aff2 = MPIDR_AFFLVL2_VAL(target); 1148 aff3 = MPIDR_AFFLVL3_VAL(target); 1149 1150 /* 1151 * Make target list from affinity 0, and ensure GICv3 SGI can target 1152 * this PE. 1153 */ 1154 assert(aff0 < GICV3_MAX_SGI_TARGETS); 1155 tgt = BIT_32(aff0); 1156 1157 /* Raise SGI to PE specified by its affinity */ 1158 sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_num, SGIR_IRM_TO_AFF, 1159 tgt); 1160 1161 /* 1162 * Ensure that any shared variable updates depending on out of band 1163 * interrupt trigger are observed before raising SGI. 1164 */ 1165 dsbishst(); 1166 write_icc_sgi0r_el1(sgi_val); 1167 isb(); 1168 } 1169 1170 /******************************************************************************* 1171 * This function sets the interrupt routing for the given (E)SPI interrupt id. 1172 * The interrupt routing is specified in routing mode and mpidr. 1173 * 1174 * The routing mode can be either of: 1175 * - GICV3_IRM_ANY 1176 * - GICV3_IRM_PE 1177 * 1178 * The mpidr is the affinity of the PE to which the interrupt will be routed, 1179 * and is ignored for routing mode GICV3_IRM_ANY. 1180 ******************************************************************************/ 1181 void gicv3_set_spi_routing(unsigned int id, unsigned int irm, u_register_t mpidr) 1182 { 1183 unsigned long long aff; 1184 uint64_t router; 1185 1186 assert(gicv3_driver_data != NULL); 1187 assert(gicv3_driver_data->gicd_base != 0U); 1188 1189 assert((irm == GICV3_IRM_ANY) || (irm == GICV3_IRM_PE)); 1190 1191 assert(IS_SPI(id)); 1192 1193 aff = gicd_irouter_val_from_mpidr(mpidr, irm); 1194 gicd_write_irouter(gicv3_driver_data->gicd_base, id, aff); 1195 1196 /* 1197 * In implementations that do not require 1 of N distribution of SPIs, 1198 * IRM might be RAZ/WI. Read back and verify IRM bit. 1199 */ 1200 if (irm == GICV3_IRM_ANY) { 1201 router = gicd_read_irouter(gicv3_driver_data->gicd_base, id); 1202 if (((router >> IROUTER_IRM_SHIFT) & IROUTER_IRM_MASK) == 0U) { 1203 ERROR("GICv3 implementation doesn't support routing ANY\n"); 1204 panic(); 1205 } 1206 } 1207 } 1208 1209 /******************************************************************************* 1210 * This function clears the pending status of an interrupt identified by id. 1211 * The proc_num is used if the interrupt is SGI or (E)PPI, and programs the 1212 * corresponding Redistributor interface. 1213 ******************************************************************************/ 1214 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num) 1215 { 1216 assert(gicv3_driver_data != NULL); 1217 assert(gicv3_driver_data->gicd_base != 0U); 1218 assert(proc_num < gicv3_driver_data->rdistif_num); 1219 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1220 1221 /* 1222 * Clear pending interrupt, and ensure that any shared variable updates 1223 * depending on out of band interrupt trigger are observed afterwards. 1224 */ 1225 1226 /* Check interrupt ID */ 1227 if (is_sgi_ppi(id)) { 1228 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1229 gicr_set_icpendr( 1230 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1231 } else { 1232 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1233 gicd_set_icpendr(gicv3_driver_data->gicd_base, id); 1234 } 1235 1236 dsbishst(); 1237 } 1238 1239 /******************************************************************************* 1240 * This function sets the pending status of an interrupt identified by id. 1241 * The proc_num is used if the interrupt is SGI or PPI and programs the 1242 * corresponding Redistributor interface. 1243 ******************************************************************************/ 1244 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num) 1245 { 1246 assert(gicv3_driver_data != NULL); 1247 assert(gicv3_driver_data->gicd_base != 0U); 1248 assert(proc_num < gicv3_driver_data->rdistif_num); 1249 assert(gicv3_driver_data->rdistif_base_addrs != NULL); 1250 1251 /* 1252 * Ensure that any shared variable updates depending on out of band 1253 * interrupt trigger are observed before setting interrupt pending. 1254 */ 1255 dsbishst(); 1256 1257 /* Check interrupt ID */ 1258 if (is_sgi_ppi(id)) { 1259 /* For SGIs: 0-15, PPIs: 16-31 and EPPIs: 1056-1119 */ 1260 gicr_set_ispendr( 1261 gicv3_driver_data->rdistif_base_addrs[proc_num], id); 1262 } else { 1263 /* For SPIs: 32-1019 and ESPIs: 4096-5119 */ 1264 gicd_set_ispendr(gicv3_driver_data->gicd_base, id); 1265 } 1266 } 1267 1268 /******************************************************************************* 1269 * This function sets the PMR register with the supplied value. Returns the 1270 * original PMR. 1271 ******************************************************************************/ 1272 unsigned int gicv3_set_pmr(unsigned int mask) 1273 { 1274 unsigned int old_mask; 1275 1276 old_mask = (unsigned int)read_icc_pmr_el1(); 1277 1278 /* 1279 * Order memory updates w.r.t. PMR write, and ensure they're visible 1280 * before potential out of band interrupt trigger because of PMR update. 1281 * PMR system register writes are self-synchronizing, so no ISB required 1282 * thereafter. 1283 */ 1284 dsbishst(); 1285 write_icc_pmr_el1(mask); 1286 1287 return old_mask; 1288 } 1289 1290 /******************************************************************************* 1291 * This function delegates the responsibility of discovering the corresponding 1292 * Redistributor frames to each CPU itself. It is a modified version of 1293 * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform 1294 * unlike the previous way in which only the Primary CPU did the discovery of 1295 * all the Redistributor frames for every CPU. It also handles the scenario in 1296 * which the frames of various CPUs are not contiguous in physical memory. 1297 ******************************************************************************/ 1298 int gicv3_rdistif_probe(const uintptr_t gicr_frame) 1299 { 1300 u_register_t mpidr; 1301 unsigned int proc_num, proc_self; 1302 uint64_t typer_val; 1303 uintptr_t rdistif_base; 1304 bool gicr_frame_found = false; 1305 1306 assert(gicv3_driver_data->gicr_base == 0U); 1307 1308 /* Ensure this function is called with Data Cache enabled */ 1309 #ifndef __aarch64__ 1310 assert((read_sctlr() & SCTLR_C_BIT) != 0U); 1311 #else 1312 assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U); 1313 #endif /* !__aarch64__ */ 1314 1315 proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1()); 1316 rdistif_base = gicr_frame; 1317 do { 1318 typer_val = gicr_read_typer(rdistif_base); 1319 if (gicv3_driver_data->mpidr_to_core_pos != NULL) { 1320 mpidr = mpidr_from_gicr_typer(typer_val); 1321 proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr); 1322 } else { 1323 proc_num = (unsigned int)(typer_val >> 1324 TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK; 1325 } 1326 if (proc_num == proc_self) { 1327 /* The base address doesn't need to be initialized on 1328 * every warm boot. 1329 */ 1330 if (gicv3_driver_data->rdistif_base_addrs[proc_num] 1331 != 0U) { 1332 return 0; 1333 } 1334 gicv3_driver_data->rdistif_base_addrs[proc_num] = 1335 rdistif_base; 1336 gicr_frame_found = true; 1337 break; 1338 } 1339 rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT); 1340 } while ((typer_val & TYPER_LAST_BIT) == 0U); 1341 1342 if (!gicr_frame_found) { 1343 return -1; 1344 } 1345 1346 /* 1347 * Flush the driver data to ensure coherency. This is 1348 * not required if platform has HW_ASSISTED_COHERENCY 1349 * enabled. 1350 */ 1351 #if !HW_ASSISTED_COHERENCY 1352 /* 1353 * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver. 1354 */ 1355 flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]), 1356 sizeof(*(gicv3_driver_data->rdistif_base_addrs))); 1357 #endif 1358 return 0; /* Found matching GICR frame */ 1359 } 1360 1361 /****************************************************************************** 1362 * This function checks the interrupt ID and returns true for SGIs and (E)PPIs 1363 * and false for (E)SPIs IDs. 1364 *****************************************************************************/ 1365 static bool is_sgi_ppi(unsigned int id) 1366 { 1367 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */ 1368 if (IS_SGI_PPI(id)) { 1369 return true; 1370 } 1371 1372 /* SPIs: 32-1019, ESPIs: 4096-5119 */ 1373 if (IS_SPI(id)) { 1374 return false; 1375 } 1376 1377 assert(false); 1378 panic(); 1379 } 1380