feat(juno): boot with TRANSFER_LIST

This patch supports booting with TRANSFER_LIST option in juno board.

Change-Id: I6d5a8c765291c301cf1e25e1ce12d0f7058979c7
Signed-off-by: Yeoreum Yun <yeoreum.yun

feat(juno): boot with TRANSFER_LIST

This patch supports booting with TRANSFER_LIST option in juno board.

Change-Id: I6d5a8c765291c301cf1e25e1ce12d0f7058979c7
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): organize juno_stmm_manifest.dts

To generalize manifest file for StandaloneMm for juno board,
organize this manifest file with stmm_*.dtsi.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.co

feat(juno): organize juno_stmm_manifest.dts

To generalize manifest file for StandaloneMm for juno board,
organize this manifest file with stmm_*.dtsi.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I138e01b8327fa0136ca255c213bf846de7229f23

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feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

Ho

feat(fvp): increase PLAT_ARM_SPMC_SIZE for rust-spmc

rust-spmc [0] which is experimental S-EL1 SPMC uses
PLAT_ARM_TRUSTED_DRAM area to run itself as much as
16MB (half of PLAT_ARM_TRUSTED_DRAM).

However since PLAT_ARM_SPMC_SIZE is defined as 2MB,
the memory layout specified in arm_spm_def.h defines wrong value.
(i.e) PLAT_SPM_BUF_BASE, secure crb buffer and etc.

To resolve this increase the PLAT_ARM_SPMC_SIZE to 16MB.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ief207d787dd83e7a8e3c55f39fbc25d964ee8b25

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feat(fvp): add StandaloneMm manifest for rust-spmc

The rust-spmc [0] is the BL32 binary which is
SPMC in S-EL1 (experimental).
This patch adds StandaloneMm manifest file used with rust spmc.

Link:

feat(fvp): add StandaloneMm manifest for rust-spmc

The rust-spmc [0] is the BL32 binary which is
SPMC in S-EL1 (experimental).
This patch adds StandaloneMm manifest file used with rust spmc.

Link: https://git.trustedfirmware.org/rust-spmc/rust-spmc.git [0]
Change-Id: I9e79c001257647d4243a1177fe9796f664788406
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces

refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces duplication and simplifies control over SPSR
generation for later stages, particularly BL33.

The SPD remains responsible for setting the SPSR for BL32.

Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Document

feat(fvp): enable kernel dt convention

Enable USE_KERNEL_DT_CONVENTION for the FVP platform to pass the DT blob
(DTB) in x0 to BL33. This aligns with the Linux boot protocol as
described in Documentation/arm64/booting.rst.

In addition:

- Clean up legacy ARM_LINUX_KERNEL_AS_BL33 handling since
USE_KERNEL_DT_CONVENTION now implies this mode for DT handoff.
- Override args.arg0 for BL33 to point to ARM_PRELOADED_DTB_BASE in
RESET_TO_BL31.
- Skip setting the primary MPID in x0 when using this convention.

Change-Id: Ieea8cfe68104b82038b9311613abf13afe7b48f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by

feat(fvp): organize fvp_stmm_manifest.dts

To generalize manifest file for StandaloneMm for FVP,
organize this manifest file by separating:

* stmm_common.dtsi
- collection of macros to used by {plat_}stmm_*.dts(i) files.

* stmm_dev_region.dtsi
- device region template for StandaloneMm.
- If some environment don't required it, it can be excluded in
by not defining STMM_XXX macro.

* stmm_mem_region.dtsi
- memory region template for StandaloneMm.

* stmm_template.dts
- StandaloneMm manifest template defining common root node
information.

* fvp_stmm_{xxx}_manifest.dts
- Main StandaloneMm manifest file.
- According to environment, defines proper STMM_XXX value
to define device/memory region.
- device region can be excluded by not defining some STMM_XXX macro.

This is useful to define new StandaloneMm manifest
in different environments.

Change-Id: Ia9668c4994f589b178872d4d7a18a9f28075df74
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): add pseudo CRB area

To support StnadlaoneMm with fTPM, add pseudo CRB area used by fTPM.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I8959faf0b222c326fefedf3f809cc96c276

feat(juno): add pseudo CRB area

To support StnadlaoneMm with fTPM, add pseudo CRB area used by fTPM.

Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I8959faf0b222c326fefedf3f809cc96c276a769b

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feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.

feat(fvp): add pseudo CRB area

To support StandaloneMm with fTPM, add pseudo CRB area used by fTPM.

Change-Id: I43fd00dd23b0f4e6dbc8859808633a0c6051c8b6
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): increase xtable for pseudo CRB

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TAB

feat(juno): increase xtable for pseudo CRB

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I0a41b2f9ab127cc10c213fd1216a6fdd2e0ab850
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMA

feat(fvp): increase xtable for pseudo CRB for SPMC_AT_EL3

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPMC_AT_EL3 need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: I4c3cbf6242f2ccf154b93e9497ab9a21a4b67772
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIF

feat(fvp): tos_fw_config with transfer list

To load bl32's secure parition, tos_fw_config should be passed
via transfer list with DT_FFA_MANIFEST entry.

For this:
1. define PLAT_ARM_SPMC_SP_MANIFEST_SIZE with PAGE_SIZE taken
from PLAT_ARM_HW_CONFIG_SIZE by reducing it as amount of
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

2. increase HAND_OFF transfer list size as much as
PLAT_ARM_SPMC_SP_MANIFEST_SIZE.

Change-Id: I56be7783ee4d257e33148f1f623a64bc498f1955
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3

Load tos_fw_cfg when SPMC_AT_EL3 enabled and deliver its manifest
via transfer list and set its address in entrypoint's arg0 to load it
prope

feat(arm): load tos_fw_cfg using xferlist in SPMC_AT_EL3

Load tos_fw_cfg when SPMC_AT_EL3 enabled and deliver its manifest
via transfer list and set its address in entrypoint's arg0 to load it
properly by spmc_setup().

Change-Id: I43490d0bbe8288701efcce93313838395d41f330
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off

feat(fvp): increase secure partition's table mapping count

For tpm event log event region passed to SP,
increase table mapping count.

Change-Id: Ie9f899a611b6715ea9a8bd3f532774d3f8f6955e
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length

feat(fvp): increase bl2 mmap tables for handoff

With firmware handoff and SPMC_AT_EL3, the BL2 translation tables
need to be one entry longer than they currently are.
Increase the current max length by this much to allow to
build these two configurations together.

Change-Id: Ifaeee5010143b53ba4f43c45011eaa8a28456bc5
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLA

feat(fvp): increase xtable for pseudo CRB for SPM_MM

As normal pseudo CRB is allocated in DRAM1 area,
spmc running with SPM_MM need more subtable to map this area.
So, increase PLAT_SP_IMAGE_MAX_XLAT_TABLES

Change-Id: If48e2eb90e3d4319b0588e4467f2bda0fbaf9a64
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Li

feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I638fd7346853894d3377d63fc7fb4daf48415602

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feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be co

feat(fvp): add extra DRAM configuration for TZC

As number of ARM_TZC_REGIONS_DEF is reduced by moving
PLAT_SP_IMAGE_NS_BUF_BASE into NS_DRAM1 area [0],
in SPM_MM or SPMC_AT_EL3, extra DRAM can be configured in TZC.

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I08e01016f0f4c534e08744117f36fb1fbd1b6e04

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feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Lin

feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: Ic784dfcce921182968854a0fc90487754a8f59c8

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feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SI

feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I421b1f1283600de81024c7415af9919c9afbe138

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feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link

feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE

As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)

Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I6e97954a1ce91fdbda4edcdba5ccfa1d7c8ff475

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Merge changes from topic "ar/soc_name" into integration

* changes:
feat(fvp): add SoC name support to FVP
feat(smccc): add SoC name support to SMCCC_ARCH_SOC_ID

feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Re

feat(fvp): add SoC name support to FVP

This patch adds support in the FVP platform for the SoC name
field in SMCCC_ARCH_SOC_ID. The returned string is formatted as:

"Arm Platform Revision <SoC Revision>"

This adheres to the guideline that the SoC name must not expose
information beyond what is already captured in <SoC Version, SoC
Revision>.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I83da745a754c6fc8f9fa27ee8d8024d6692d3409

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feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by n

feat(juno): support StandaloneMm

Support StandaloneMm in Juno platform.
When Juno using StandaloneMm, last 2MB area of norflash0 is used by
StandaloneMm only and that area shouldn't be accessed by normal world.
For this, add last 2MB area of norflash0 in TZC setting.

Change-Id: Ice63f13c34f452f2b8cb93ee88dc666632b84248
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>

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fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a diff

fix(arm): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The condition is explicitly checked against 0U, appending 'U' and
typecasting for unsigned comparison.

Change-Id: I04089721d124a2701e10d3f6e0ed8f82e3f6e0b3
Signed-off-by: Saivardhan Thatikonda <saivardhan.thatikonda@amd.com>

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