refactor(neoverse-rd): remove inclusion of nrd_base_platform_def.h

The platform_def.h file includes the nrd_base_platform_def.h file in its
hierarchy of file inclusions. So the source files that inc

refactor(neoverse-rd): remove inclusion of nrd_base_platform_def.h

The platform_def.h file includes the nrd_base_platform_def.h file in its
hierarchy of file inclusions. So the source files that include
platform_def.h file do not have to include the nrd_base_platform_def.h
file. So remove such explicit inclusion of nrd_base_platform_def.h from
the source files. The scope of this change is limited to only the first
generation of the reference design platforms, that is, the A75, N1 and
V1 based platforms.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I088b9f0ccfd9f94b5bb3c8ed91c23e8994484c7c

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refactor(neoverse-rd): header files for first generation platforms

Presently, platforms such as SGI-575, RD-N1-Edge single and dual chip,
RD_V1 single and multi-chip utilize nrd_soc_platform_def.h a

refactor(neoverse-rd): header files for first generation platforms

Presently, platforms such as SGI-575, RD-N1-Edge single and dual chip,
RD_V1 single and multi-chip utilize nrd_soc_platform_def.h and
nrd_soc_css_def.h for all css and soc-related defines. So move these
two header files into a new directory named 'nrd1'. This new directory
will serve as the container of header files that are specific to
SGI-575, RD-N1 and RD-V1 platform and its variants.

Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9d70659c6f5000ad6c1cfc0738f9e81f03238f5f

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refactor(fvp_r): remove duplicated macro definitions

The system counter macros are defined duplicatedly in the header file.
As the macros must be defined before arm_def.h, this patch removes the
red

refactor(fvp_r): remove duplicated macro definitions

The system counter macros are defined duplicatedly in the header file.
As the macros must be defined before arm_def.h, this patch removes the
redundant definitions afterwards.

Change-Id: Id74a8ef1b9cec4a978366b6db69981cfc30dffb6
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(fvp): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id

refactor(fvp): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I36b8e498f3226fc72d21634aae2cc9328d00711d

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refactor(fvp): remove leftovers from rss measured boot support

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I1687327e028c2baec1ac6f0ae21b42b6047ceac0

refactor(tc): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id:

refactor(tc): change all occurrences of RSS to RSE

Changes all occurrences of "RSS" and "rss" in the code and build files
to "RSE" and "rse".

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Idec0bf7a90ae381f5bc968e1bb167daace24a11f

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refactor(tc): rename all 'rss' files to 'rse'

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I264690e9bbc30be7ed7b8e4e165696494a67e00c

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add th

fix(spm): add device-regions used in tf-a-tests

Device memory region specified in an SP manifest are now validated
against the device memory defined in the SPMC manifest. Therefore
we need to add the device memory used in the tf-a-tests to the SPMC
manifests.

Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
Change-Id: I47376e67c700705d12338d7078292618a15d5546

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fix: static checks on spmc dts

Change the header of the license to have 2024, and
replace spaces for a tab.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348

fix: static checks on spmc dts

Change the header of the license to have 2024, and
replace spaces for a tab.

Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: If98161ad35e1ead30e1e0d3ddb4cc6348e83d6ee

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Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only

Merge changes from topic "lto-fixes" into integration

* changes:
fix(bl1): add missing `__RW_{START,END}__` symbols
fix(fvp): don't check MPIDRs with the power controller in BL1
fix(arm): only expose `arm_bl2_dyn_cfg_init` to BL2
fix(cm): hide `cm_init_context_by_index` from BL1
fix(bl1): add missing spinlock dependency

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Merge changes from topic "hm/handoff" into integration

* changes:
refactor(fvp): reduce max size of HW_CONFIG to 16KB
refactor(arm): replace hard-coded HW_CONFIG DT size

Merge "fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest" into integration

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both n

refactor(fvp): reduce max size of HW_CONFIG to 16KB

HW_CONFIG is the hardware description consumed primarly by the Linux
kernel, and for the FVP platform, TF-A runtime firmware (BL31). Due to
both needing it, two copies of this file are made in Trusted DRAM and
SRAM. The copy in Trusted DRAM is a workaround stemming from memory
constraints in SRAM. We temporarily map the range of memory in Trusted
DRAM into BL31 to allow it to consume the configuration. In principle,
however, BL31 execution should be limited to SRAM, hence reduce the
maximum size of the HW_CONFIG to 16KB in order to accommodate it in
SRAM. This is possible since in practice, the HW_CONFIG on FVP is only
about 11KB.

Change-Id: Idb5dc0637b402562b7177a2b4e2464c4f3f67da7
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717

refactor(arm): replace hard-coded HW_CONFIG DT size

Ensure consistency across all Arm platforms, even those that may already
have an existing macro for this purpose.

Change-Id: I07cd4cfcacf2c991717f4c115cb0babd2c614d6f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing i

fix(fvp): don't check MPIDRs with the power controller in BL1

The core platform layer requires an implementation for the
`plat_core_pos_by_mpidr` function. This implementation is currently
missing in BL1, which causes undefined reference errors when linking
with LTO.

The FVP platform source file providing this implementation is the
`fvp_topology.c` file, so this change adds it to the BL1 sources for the
FVP.

However, the implementation of this function reaches out to the FVP
power controller driver - `fvp_pm.c` - to validate the MPIDR, and this
file has at least two other dependencies:

- `spe.c`
- `arm_gicvX.c`

Pulling these in correctly is no simple job, so I am simply removing the
power controller validation in BL1 builds.

Change-Id: I56ddf1d799f5fe7f5b0fb2b046f7fe8232b07b27
Signed-off-by: Chris Kay <chris.kay@arm.com>

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fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest

FFA_RXTX_MAP now requires the buffers to be in non-secure memory. This
patch ensures that a region of non-secure memory is available so th

fix(ff-a): add NS memory node to fvp_spmc_optee_sp manifest

FFA_RXTX_MAP now requires the buffers to be in non-secure memory. This
patch ensures that a region of non-secure memory is available so that
tftf tests can pass.

Change-Id: I9daf3182e0dcb73d2bf5a5baffb1b4b78c724dcb
Signed-off-by: Karl Meakin <karl.meakin@arm.com>

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Merge "refactor(arm): remove unused SP_MIN UART macros" into integration

feat(rme): pass console info via RMM-EL3 ifc

This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.

Boot manifest version is bumped to v0.3

Signed-off-by: H

feat(rme): pass console info via RMM-EL3 ifc

This patch modifies the boot manifest to add console information to
be passed from EL3 to RMM.

Boot manifest version is bumped to v0.3

Signed-off-by: Harry Moulton <harry.moulton@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Iedc4e640fb7a4450ce5ce966ae76936d1b7b742d

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refactor(arm): remove unused SP_MIN UART macros

Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, a

refactor(arm): remove unused SP_MIN UART macros

Currently, tf-a has been refactored to support the multi UARTs (boot and
runtime UARTs). As a result, the SP_MIN UART related code has been
removed, and the macros are no longer used.

Therefore, this patch removes these unused UART macros.

Change-Id: I496349f876ba918fcafa7ed6c65d149914762290
Signed-off-by: Leo Yan <leo.yan@arm.com>

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refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently cont

refactor(mte): remove mte, mte_perm

Currently both FEAT_MTE and FEAT_MTE_PERM aren't used for enabling
of any feature bits in EL3. So remove both FEAT handling.

All mte regs that are currently context saved/restored are needed
only when FEAT_MTE2 is enabled, so move to usage of FEAT_MTE2 and
remove FEAT_MTE usage.

BREAKING CHANGE: Any platform or downstream code trying to use
SCR_EL3.ATA bit(26) will see failures as this is now moved to be
used only with FEAT_MTE2 with
commit@ef0d0e5478a3f19cbe70a378b9b184036db38fe2

Change-Id: Id01e154156571f7792135639e17dc5c8d0e17cf8
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE

fix(cpus): workaround for Cortex-A720 erratum 2926083

Cortex-A720 erratum 2926083 is a Cat B erratum that is present
in revisions r0p0, r0p1 and is fixed in r0p2. The errata is only
present when SPE (Statistical Profiling Extension) is implemented
and enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is "implemented and enabled".

SDEN documentation:
https://developer.arm.com/documentation/SDEN2439421/latest

Change-Id: I30182c3893416af65b55fca9a913cb4512430434
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(S

fix(cpus): workaround for Cortex-A715 erratum 2413290

Cortex-A715 erratum 2413290 is a Cat B erratum that is present
only in revision r1p0 and is fixed in r1p1. The errata is only
present when SPE(Statistical Profiling Extension) is enabled.

The workaround is to set bits[58:57] of the CPUACTLR_EL1 to 'b11
when SPE is enabled, ENABLE_SPE_FOR_NS=1.

SDEN documentation:
https://developer.arm.com/documentation/SDEN2148827/latest

Change-Id: Iaeb258c8b0a92e93d70b7dad6ba59d1056aeb135
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>

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Merge "refactor(cm): couple el2 registers with dependent feature flags" into integration

Merge "fix(tc): do not use r0 for HW_CONFIG" into integration

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level for region validity
feat(tc): add dummy TRNG support to be able to boot pVMs
feat(tc): get the parent component provided DPE context_handle
feat(tc): share DPE context handle with child component
feat(tc): add DPE context handle node to device tree
feat(tc): add DPE backend to the measured boot framework
feat(auth): add explicit entries for key OIDs
feat(dice): add DPE driver to measured boot
feat(dice): add client API for DICE Protection Environment
feat(dice): add QCBOR library as a dependency of DPE
feat(dice): add typedefs from the Open DICE repo
docs(changelog): add 'dice' scope
refactor(tc): align image identifier string macros
refactor(fvp): align image identifier string macros
refactor(imx8m): align image identifier string macros
refactor(qemu): align image identifier string macros
fix(measured-boot): add missing image identifier string
refactor(measured-boot): move metadata size macros to a common header
refactor(measured-boot): move image identifier strings to a common header

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