| ca932481 | 10-Mar-2021 |
Davidson K <davidson.kumaresan@arm.com> |
feat(tc0): add support for trusted services
This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by
feat(tc0): add support for trusted services
This patch adds support for the crypto and secure storage secure
partitions for the Total Compute platform. These secure partitions
have to be managed by Hafnium executing at S-EL2
Change-Id: I2df690e3a99bf6bf50e2710994a905914a07026e
Signed-off-by: Davidson K <davidson.kumaresan@arm.com>
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| e8b119e0 | 23-Mar-2021 |
Pranav Madhu <pranav.madhu@arm.com> |
feat(plat/sgi): enable AMU for RD-V1-MC
AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure O
feat(plat/sgi): enable AMU for RD-V1-MC
AMU counters are used for monitoring the CPU performance. RD-V1-MC
platform has architected AMU available for each core. Enable the use of
AMU by non-secure OS for supporting the use of counters for processor
performance control (ACPI CPPC).
Change-Id: I33be594cee669e7f4031e5e5a371eec7c7451030
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
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| 6794378d | 29-Apr-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes from topic "fw-update" into integration
* changes:
docs: add build options for GPT support enablement
feat(plat/arm): add GPT parser support |
| ef1daa42 | 22-Feb-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
feat(plat/arm): add GPT parser support
Added GPT parser support in BL2 for Arm platforms to get the entry
address and length of the FIP in the GPT image.
Also, increased BL2 maximum size for FVP pl
feat(plat/arm): add GPT parser support
Added GPT parser support in BL2 for Arm platforms to get the entry
address and length of the FIP in the GPT image.
Also, increased BL2 maximum size for FVP platform to successfully
compile ROM-enabled build with this change.
Verified this change using a patch:
https://review.trustedfirmware.org/c/ci/tf-a-ci-scripts/+/9654
Change-Id: Ie8026db054966653b739a82d9ba106d283f534d0
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| 800b8849 | 28-Apr-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "refactor(plat/arm): replace FIP base and size macro with a generic name" into integration |
| 7d111d99 | 08-Apr-2021 |
David Horstmann <david.horstmann@arm.com> |
refactor(plat/arm): store UUID as a string, rather than ints
NOTE: Breaking change to the way UUIDs are stored in the DT
Currently, UUIDs are stored in the device tree as
sequences of 4 integers. T
refactor(plat/arm): store UUID as a string, rather than ints
NOTE: Breaking change to the way UUIDs are stored in the DT
Currently, UUIDs are stored in the device tree as
sequences of 4 integers. There is a mismatch in endianness
between the way UUIDs are represented in memory and the way
they are parsed from the device tree. As a result, we must either
store the UUIDs in little-endian format in the DT (which means
that they do not match up with their string representations)
or perform endianness conversion after parsing them.
Currently, TF-A chooses the second option, with unwieldy
endianness-conversion taking place after reading a UUID.
To fix this problem, and to make it convenient to copy and
paste UUIDs from other tools, change to store UUIDs in string
format, using a new wrapper function to parse them from the
device tree.
Change-Id: I38bd63c907be14e412f03ef0aab9dcabfba0eaa0
Signed-off-by: David Horstmann <david.horstmann@arm.com>
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| 49e9ac28 | 22-Apr-2021 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
refactor(plat/arm): replace FIP base and size macro with a generic name
Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a
generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IM
refactor(plat/arm): replace FIP base and size macro with a generic name
Replaced PLAT_ARM_FIP_BASE and PLAT_ARM_FIP_MAX_SIZE macro with a
generic name PLAT_ARM_FLASH_IMAGE_BASE and PLAT_ARM_FLASH_IMAGE_MAX_SIZE
so that these macros can be reused in the subsequent GPT based support
changes.
Change-Id: I88fdbd53e1966578af4f1e8e9d5fef42c27b1173
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| fe5d5bbf | 20-Mar-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
feat(board/rdn2): add support for variant 1 of rd-n2 platform
Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a
variant of RD-N2 platform with a reduced interconnect mesh size (3x3
feat(board/rdn2): add support for variant 1 of rd-n2 platform
Add board support for RD-N2 Cfg1 variant of RD-N2 platform. It is a
variant of RD-N2 platform with a reduced interconnect mesh size (3x3)
and core count (8-cores). Its platform variant id is 1.
Change-Id: I34ad35c5a5c1e9b69a658fb92ed00e5bc5fe72f3
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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| cfe1506e | 20-Mar-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
feat(plat/sgi): introduce platform variant build option
A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reu
feat(plat/sgi): introduce platform variant build option
A Neoverse reference design platform can have two or more variants that
differ in core count, cluster count or other peripherals. To allow reuse
of platform code across all the variants of a platform, introduce build
option CSS_SGI_PLATFORM_VARIANT for Arm Neoverse reference design
platforms. The range of allowed values for the build option is platform
specific. The recommended range is an interval of non negative integers.
An example usage of the build option is
make PLAT=rdn2 CSS_SGI_PLATFORM_VARIANT=1
Change-Id: Iaae79c0b4d0dc700521bf6e9b4979339eafe0359
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
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|
| 303f543e | 26-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "sgm775_deprecation" into integration
* changes:
build: deprecate Arm sgm775 FVP platform
docs: introduce process for platform deprecation |
| c404794a | 14-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: move compile time switch from source to dt file
This will help in keeping source file generic and conditional
compilation can be contained in platform provided dt files.
Signed-off-by: Ma
plat/arm: move compile time switch from source to dt file
This will help in keeping source file generic and conditional
compilation can be contained in platform provided dt files.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I3c6e0a429073f0afb412b9ba521ce43f880b57fe
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| 7bcb8ad2 | 26-Apr-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "Arm: Fix error message printing in board makefile" into integration |
| 37ee58d1 | 22-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
build: deprecate Arm sgm775 FVP platform
sgm775 is an old platform and is no longer maintained by Arm and its
fast model FVP_CSS_SGM-775 is no longer available for download.
This platform is now sup
build: deprecate Arm sgm775 FVP platform
sgm775 is an old platform and is no longer maintained by Arm and its
fast model FVP_CSS_SGM-775 is no longer available for download.
This platform is now superseded by Total Compute(tc) platforms.
This platform is now deprecated but the source will be kept for cooling
off period of 2 release cycle before removing it completely.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I8fe1fc3da0c508dba62ed4fc60cbc1642e0f7f2a
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|
| dfe64665 | 21-Apr-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add "_arm" suffix to Makalu ELP CPU lib" into integration |
| 97bc7f0d | 20-Apr-2021 |
johpow01 <john.powell@arm.com> |
Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from othe
Add "_arm" suffix to Makalu ELP CPU lib
ELP processors can sometimes have different MIDR values or features so
we are adding the "_arm" suffix to differentiate the reference
implementation from other future versions.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20
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| 5d5fb10f | 12-Feb-2021 |
Mikael Olsson <mikael.olsson@arm.com> |
plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been
plat/arm/juno: Add support to use hw_config in BL31
To make it possible to use the hw_config device tree for dynamic
configuration in BL31 on the Arm Juno platform. A placeholder hw_config
has been added that is included in the FIP and a Juno specific BL31
setup has been added to populate fconf with the hw_config.
Juno's BL2 setup has been updated to align it with the new behavior
implemented in the Arm FVP platform, where fw_config is passed in arg1
to BL31 instead of soc_fw_config. The BL31 setup is expected to use the
fw_config passed in arg1 to find the hw_config.
Signed-off-by: Mikael Olsson <mikael.olsson@arm.com>
Change-Id: Ib3570faa6714f92ab8451e8f1e59779dcf19c0b6
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| 5eea0193 | 16-Apr-2021 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Arm: Fix error message printing in board makefile
Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:
plat/a
Arm: Fix error message printing in board makefile
Remove an incorrect tabulation in front of an $(error) function call
outside of a recipe, which caused the following text to be displayed:
plat/arm/board/common/board_common.mk:36: *** recipe commences before first target. Stop.
instead of:
plat/arm/board/common/board_common.mk:36: *** "Unsupported ARM_ROTPK_LOCATION value". Stop.
Change-Id: I8592948e7de8ab0c4abbc56eb65a53eb1875a83c
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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|
| 866e6721 | 15-Apr-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "scmi_v2_0" into integration
* changes:
drivers/arm/css/scmi: Update power domain protocol version to 2.0
tc0: update GICR base address |
| 69f2ace1 | 30-Mar-2021 |
Usama Arif <usama.arif@arm.com> |
tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642
tc0: update GICR base address
The number of ITS have changed from 4 to 1, resulting
in GICR base address change.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
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|
| 3b9e06a6 | 13-Apr-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "plat/arm: don't provide NT_FW_CONFIG when booting hafnium" into integration |
| 2b6fc535 | 09-Apr-2021 |
Manish Pandey <manish.pandey2@arm.com> |
plat/arm: don't provide NT_FW_CONFIG when booting hafnium
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the
plat/arm: don't provide NT_FW_CONFIG when booting hafnium
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by
BL33, fvp platforms use this to pass measured boot configuration and
the x0 register is used to pass the base address of it.
In case of hafnium used as hypervisor in normal world, hypervisor
manifest is expected to be passed from BL31 and its base address is
passed in x0 register.
As only one of NT_FW_CONFIG or hypervisor manifest base address can be
passed in x0 register and also measured boot is not required for SPM so
disable passing NT_FW_CONFIG.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e
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| 0a144dd4 | 16-Mar-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Add Cortex_A78C CPU lib
Add basic support for Cortex_A78C CPU.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56 |
| e5fa7459 | 29-Mar-2021 |
bipin.ravi <bipin.ravi@arm.com> |
Merge "Add Makalu ELP CPU lib" into integration |
| f97b5795 | 17-Feb-2021 |
Aditya Angadi <aditya.angadi@arm.com> |
board/rdv1mc: initialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM m
board/rdv1mc: initialize tzc400 controllers
A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
across the Chips.
For use by secure software, configure the first chip's trustzone
controller to protect the upper 16MB of the memory of the first DRAM
block for secure accesses only. The other regions are configured for
non-secure read write access. For all the remote chips, all the DRAM
regions are allowed for non-secure read and write access.
Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
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| b4d548f1 | 16-Feb-2021 |
Thomas Abraham <thomas.abraham@arm.com> |
plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
plat/sgi: define default list of memory regions for dmc620 tzc
Define a default DMC-620 TZC memory region configuration and use it to
specify the TZC memory regions on sgi575, rdn1edge and rde1edge
platforms. The default DMC-620 TZC memory regions are defined
considering the support for secure paritition as well.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: Iedee3e57d0d3de5b65321444da51ec990d3702db
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