feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the buil

feat(corstone-1000): add Cortex-A320 support

Introduce `CORSTONE1000_CORTEX_A320` to enable Cortex-A320 on
Corstone-1000 while keeping Cortex-A35 as the default. When the
define is enabled, the build switches from `cortex_a35.S` to
`cortex_a320.S`, maintaining compatibility with existing A35-based
designs.

Also add Normal-World mappings for the Ethos-U85 NPU and its SRAM
on Cortex-A320 platforms so U-Boot and other non-secure software
can safely access these regions:

* **Ethos-U85 registers**: base `0x1A050000`, size `0x00004000` (16 KB),
attrs `MT_DEVICE | MT_RW | MT_NS`
* **Non-secure SRAM**: base `0x02400000`, size `0x00400000` (4 MB),
attrs `MT_MEMORY | MT_RW | MT_NS`

Enable GICv3 with GIC-600 when building for Cortex-A320 (retain
GICv2/GIC-400 for Cortex-A35):

* Update `plat_my_core_pos()` and `plat_arm_calc_core_pos()` to use
the Cortex-A320 MPIDR_EL1 affinity layout.
* Add an A320-specific core-position routine in assembly guarded by
`CORSTONE1000_CORTEX_A320`.
* Switch to the GICv3 driver with GIC-600 extensions: update GIC base
addresses, use GICv3 APIs, and set `USE_GIC_DRIVER=3`,
`GICV3_SUPPORT_GIC600=1`, `GIC_ENABLE_V4_EXTN=1`.

These changes prepare the platform for Cortex-A320 integration and
ensure correct GIC configuration and secondary-core bring-up, while
preserving A35 behavior.

Change-Id: Ief03dd528e67918e160d5b42ad1344b0ba3440f8
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>
Signed-off-by: Frazer Carsley <frazer.carsley@arm.com>
Signed-off-by: Michael Safwat <michael.safwat@arm.com>

show more ...

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition

refactor(arm): refine FIP offset handling for BL1 with GPT support

Restrict use of PLAT_ARM_FIP_OFFSET_IN_GPT to BL1 when ARM_GPT_SUPPORT
is enabled. BL2 can derive the FIP offset from the partition table at
runtime, so a fixed offset is unnecessary. Also cleaned up the FIP
address handling comment for clarity.

Change-Id: I03f003a9307d66d16666eefcff1f45bb010779c9
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

fix(corstone1000): update memory layout comments

The SRAM (CVM) memory layout was outdated in the platform_defs.h of
the Corstone-1000 platform. Updated it to list every bootloaders and
to be aligne

fix(corstone1000): update memory layout comments

The SRAM (CVM) memory layout was outdated in the platform_defs.h of
the Corstone-1000 platform. Updated it to list every bootloaders and
to be aligned with the implementation. Also added the starting (base)
addresses of each partition.

Change-Id: Ie8e8416ee2650ff25a8d4c61d8d9af789bc639c1
Signed-off-by: Bence Balogh <bence.balogh@arm.com>

show more ...

fix(corstone1000): remove unused NS_SHARED_RAM region

After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more spa

fix(corstone1000): remove unused NS_SHARED_RAM region

After enabling additional features in Trusted Services, the size of BL32
image (OP-TEE + Trusted Services SPs) is larger now. To create more space
in secure RAM for BL32 image, this patch removes NS_SHARED_RAM region
which is not currently used by corstone1000 platform.

Change-Id: I1e9468fd2dcb66b4d21fce245097ba51331ec54d
Signed-off-by: Emekcan Aras <Emekcan.Aras@arm.com>

show more ...

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the

feat(corstone1000): add multicore support for fvp

This changeset adds the multicore support for the Corstone-1000 FVP.
It adds the PSCI CPU_ON and CPU_ON_FINISH power domain functionalities
for the secondary cores.

Change-Id: Ie66b3dc43abadec88323999052357e2a9cdfd950
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

show more ...

fix(rotpk): move rotpk definitions out of arm_def.h

The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing t

fix(rotpk): move rotpk definitions out of arm_def.h

The file arm_def.h currently contains common definitions used by ARM
platforms. However, some platforms may have their own definitions,
allowing them to avoid a direct dependency on arm_def.h. For a clean
platform port of arm_def.h, none of the source files should directly
include arm_def.h; instead, they should include the platform header
which would indirectly include the required definitions.

Presently, the rotpk module has a source file that directly includes
arm_def.h. This could lead to compilation issues if the platform
incorporating the rotpk module has a separate implementation of some or
all of the definitions in arm_def.h file. To address this, move the
relevant definitions out of arm_def.h and into rotpk_def.h.

Signed-off-by: Rohit Mathew <Rohit.Mathew@arm.com>
Change-Id: I9e8b0d319391f9a167af5c69a7b2d42ac488e7b4

show more ...

fix(corstone-1000): modify boot device dependencies

Modify boot device dependencies and remove the one's
which are not needed.

Change-Id: I71cd60558ab4bb5162afefad4f00d631c2308e72
Signed-off-by: Mo

fix(corstone-1000): modify boot device dependencies

Modify boot device dependencies and remove the one's
which are not needed.

Change-Id: I71cd60558ab4bb5162afefad4f00d631c2308e72
Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

show more ...