feat(rdaspen/ras): dump the CPER buffer contents

Print the contents of the buffer to verify the fields set.

Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagou

feat(rdaspen/ras): dump the CPER buffer contents

Print the contents of the buffer to verify the fields set.

Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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feat(rdaspen/ras): generate CPER at TF-A EL3

Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.

The CPER record consists of:
ESB Header
ESB Da

feat(rdaspen/ras): generate CPER at TF-A EL3

Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.

The CPER record consists of:
ESB Header
ESB Data Entry
CPER CPU Error Section
- Arm Processor Error Record
- Arm Processor Error Information
- Arm Processor Context Information

Change-Id: I7e9703a69edec15cbb6f0522333700bb8d7007bf
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
S

feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>

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feat(rdaspen): event handler for CPU RAS

This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.

This also enables all i

feat(rdaspen): event handler for CPU RAS

This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.

This also enables all inband errors to be handled on AP according
to a CPU RAS event handler:

- Skips spurious entries – returns early when
`ERXSTATUS.{V|CE}` is already clear, disposing of queued phantom
interrupts.

- Clears the error record – rewrites `ERXSTATUS_EL1`, zeros
`ERXMISC0`, `PFG_CTL`, and `PFG_CDN`, then logs the post clear state
for firmware trace.

Inband errors only consist of:
- Corrected Errors
- Deferred Errors

- Change the RAS CPU intr handler logs from VERBOSE to WARN.

Change-Id: I7eb8fecb42095551f51c9d1c5752775f1b577970
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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feat(rdaspen/ras): intr RAS handling for PC CPU

This introduces and enables the RAS framework and enables
the RAS for CPU handling.

This commit ensures that RAS settings are initialized on
all CPU

feat(rdaspen/ras): intr RAS handling for PC CPU

This introduces and enables the RAS framework and enables
the RAS for CPU handling.

This commit ensures that RAS settings are initialized on
all CPU cores during the firmware boot stage. Previously,
the initialization for RAS processing was only done on
the primary CPU core.

This also introduces a custom bl31_platform_setup to
allow RAS specific intialisations.

Change-Id: Ia3258aed63b8994c53ec8cc49bd27d0d907e218e
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

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