| #
b0236d0a |
| 01-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I1eb8d262,I8e3e0ce6 into integration
* changes:
docs(arm): document BL2 mem params override
feat(arm): allow custom BL2 mem params
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| #
7622cecc |
| 15-Nov-2025 |
Ahmed Azeem <ahmed.azeem@arm.com> |
feat(arm): allow custom BL2 mem params
Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this overri
feat(arm): allow custom BL2 mem params
Introduce the ARM_PLAT_PROVIDES_BL2_MEM_PARAMS flag so that
Arm platforms can supply their own bl2_mem_params_desc.c
implementation if needed. When this override is enabled,
the common arm_bl2_mem_params_desc.c implementation is
excluded from BL2_SOURCES. The platform must then append
its own bl2_mem_params_desc.c file to BL2_SOURCES.
Change-Id: I8e3e0ce6e9c2c55ec3feb18a45890f1716fe690b
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| #
39772b5f |
| 01-Dec-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I49097cc1,Iad299bf9 into integration
* changes:
docs(rdaspen): measured boot support
feat(rdaspen): enable measured boot
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| #
0bf4d2bc |
| 08-May-2025 |
Maximilian Berndt <maximilian.berndt@arm.com> |
feat(rdaspen): enable measured boot
Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.
Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f
feat(rdaspen): enable measured boot
Ports functions to support measured boot.
Additionally, add AP BL31, BL32 and BL33 to list of measured images.
Change-Id: Iad299bf902833c5472dce7eb1344f59d73a16f91
Signed-off-by: Maximilian Berndt <maximilian.berndt@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| #
9acaf99f |
| 29-Oct-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration
* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): suppo
Merge changes from topic "ahmed-azeem/rdaspen-enhancements" into integration
* changes:
fix(dsu): dsu config for all cores in hot reset
docs(rdaspen): bl32 and GPT support
feat(rdaspen): support BL32 (OP-TEE)
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| #
33a10dca |
| 19-Mar-2025 |
Archish Venkatesh <Archish.Venkatesh@arm.com> |
feat(rdaspen): support BL32 (OP-TEE)
Configure SPMC constants and Secure memory partition to boot BL32
image.
This also fixes the build to automatically accommodate BL33 if
BL32 base is not specif
feat(rdaspen): support BL32 (OP-TEE)
Configure SPMC constants and Secure memory partition to boot BL32
image.
This also fixes the build to automatically accommodate BL33 if
BL32 base is not specified, and removes a redundant entry for BL31
in platform definitions for mmap entries aswell.
Change-Id: I6a3ec97c8f41d6bddc4f20b6edc088a46e2caa75
Signed-off-by: Archish Venkatesh <Archish.Venkatesh@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| #
c0764751 |
| 24-Oct-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "ahmed-azeem/rdaspen/enhancements" into integration
* changes:
feat(rdaspen): support configurable CPU topology in device tree
feat(rdaspen): add support for configurabl
Merge changes from topic "ahmed-azeem/rdaspen/enhancements" into integration
* changes:
feat(rdaspen): support configurable CPU topology in device tree
feat(rdaspen): add support for configurable platform's CPU topology
feat(rdaspen): scmi gracefully shutdown system
feat(scmi): support graceful system power set
fix(rdaspen): enable CPU feature runtime checking
fix(rdaspen): fix timer bus cells & fix ranges
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| #
c16a3b7c |
| 28-Mar-2025 |
Amr Mohamed <amr.mohamed@arm.com> |
feat(rdaspen): add support for configurable platform's CPU topology
- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- A
feat(rdaspen): add support for configurable platform's CPU topology
- Add support for passing build time platform's CPU topology, which
defines the number of clusters and CPUs in the platform.
- Adjust the platform's power domain topology based on the passed
build time topology. If no build time topology was provided,
default topology will be used.
Change-Id: Ic80b308ab6d4c98139723021566d54be02b7d125
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
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| #
ba4814b8 |
| 19-Mar-2025 |
Jun Wu <jun.wu@arm.com> |
feat(rdaspen): scmi gracefully shutdown system
In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shu
feat(rdaspen): scmi gracefully shutdown system
In RD-Aspen, RSE shall be responsible for system shutdown. When TF-A
send a graceful SCMI system power set command to SCP, SCP will not
execute the shutdown but notify RSE runtime.
RD-Aspen enable the graceful flag of css_scp_system_off in
platform.mk.
Change-Id: I80967e1d2e85193dd98f626e4c729ac722251a53
Signed-off-by: Jun Wu <jun.wu@arm.com>
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| #
3a324c26 |
| 20-Aug-2025 |
Peter Hoyes <peter.hoyes@arm.com> |
fix(rdaspen): enable CPU feature runtime checking
Enable runtime feature detection for FEAT_AMU, FEAT_ECV, FEAT_FGT,
and FEAT_MTE2
These features were previously unconditionally enabled (=1) in the
fix(rdaspen): enable CPU feature runtime checking
Enable runtime feature detection for FEAT_AMU, FEAT_ECV, FEAT_FGT,
and FEAT_MTE2
These features were previously unconditionally enabled (=1) in the build
configuration, causing TF-A to initialize their contexts regardless of
actual CPU support in emulation implementations.
Set them to "2" to enable runtime feature detection instead.
With this change, TF-A checks the ID registers before accessing related
system registers or programming SCR_EL3 bits, avoiding register accesses
on CPUs that lack these features. This primarily addresses issues seen
in emulation environments with incomplete feature support.
Change-Id: I7f333245c60685544d925c24556358724a776082
Signed-off-by: Peter Hoyes <peter.hoyes@arm.com>
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| #
8e94c578 |
| 01-Oct-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration
* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add
Merge changes from topic "ahmed-azeem/introduce-rdaspen" into integration
* changes:
feat(dsu): enable PMU registers access at EL1
feat(rdaspen): add DSU to the device tree
feat(rdaspen): add DSU support
docs(rdaspen): introduce rdaspen docs
feat(rdaspen): enable tbb on rd-aspen platform
feat(gicv3): add GIC-720AE model id
feat(rdaspen): add BL31 for RD-Aspen platform
feat(rdaspen): introduce Arm RD-Aspen platform
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| #
d69c3b1c |
| 28-Feb-2025 |
Amr Mohamed <amr.mohamed@arm.com> |
feat(rdaspen): add DSU support
- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the
feat(rdaspen): add DSU support
- Enable use of the DSU driver through the `USE_DSU_DRIVER` flag.
This configures DSU power-down and power settings, using the
default reset values defined in the DSU-120AE TRM.
- Enable the `PRESERVE_DSU_PMU_REGS` flag to save and restore DSU
cluster PMU registers across cluster power cycles.
Change-Id: I7f820981cd164a689324a525b506c2979bddb572
Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| #
287e24f5 |
| 19-May-2025 |
Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com> |
feat(rdaspen): enable tbb on rd-aspen platform
Enable Trusted board boot on RD-Aspen platform.
Included the non-volatile(NV) memory region, to
ensure rollback protection.
Added Mbed TLS library in
feat(rdaspen): enable tbb on rd-aspen platform
Enable Trusted board boot on RD-Aspen platform.
Included the non-volatile(NV) memory region, to
ensure rollback protection.
Added Mbed TLS library initialization for MbedTLS
library.
Change-Id: I7940952c152b0243a91b38804cf16d3050ec2d4b
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
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| #
c2cd362c |
| 17-Feb-2025 |
David Hu <david.hu2@arm.com> |
feat(rdaspen): add BL31 for RD-Aspen platform
Implement BL31 for RD-Aspen platform.
* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL ima
feat(rdaspen): add BL31 for RD-Aspen platform
Implement BL31 for RD-Aspen platform.
* Implement power control features to incorporates an SCP via SCMI.
* Add the memory descriptor provides BL image information that gets
used by BL2 to load the images
Change-Id: I5f389c4a6ef9bc106b3b29c9aecbd890d91d99b3
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
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| #
d1a1abec |
| 17-Feb-2025 |
David Hu <david.hu2@arm.com> |
feat(rdaspen): introduce Arm RD-Aspen platform
Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree
This platform contains:
* C
feat(rdaspen): introduce Arm RD-Aspen platform
Create a new platform for the RD-Aspen automotive FVP.
Add the required source, header files and makefile,and
device tree
This platform contains:
* Cortex-A720AE, Armv9.2-A application processor
* A GICv4-compatible GIC-720AE
* 128 MB of SRAM, of which 512 KB is reserved for TF-A
* 4GiB of DRAM in two partitions (extensible)
It also adds:
* FW_CONFIG and HW_CONFIG device trees
Change-Id: I4ba3e4bf1fed8f3640f7eda815607b0a5cab9500
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: David Hu <david.hu2@arm.com>
Signed-off-by: Meet Patel <meet.patel2@arm.com>
show more ...
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