| #
139a5d05 |
| 18-Apr-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration
* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refacto
Merge changes I86959e67,I0b0d1d36,I5b5267f4,I056c8710,I3474aa97 into integration
* changes:
chore: fix preprocessor checks
refactor: convert arm platforms to use the generic GIC driver
refactor(gic): promote most of the GIC driver to common code
refactor: make arm_gicv2.c and arm_gicv3.c common
refactor(fvp): use more arm generic code for gicv3
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| #
c5c54e20 |
| 07-Jan-2025 |
Boyan Karatotev <boyan.karatotev@arm.com> |
refactor: convert arm platforms to use the generic GIC driver
This reduces the code the platforms have to carry and makes their build
rules a bit simpler.
The main benefit is that plat_my_core_pos(
refactor: convert arm platforms to use the generic GIC driver
This reduces the code the platforms have to carry and makes their build
rules a bit simpler.
The main benefit is that plat_my_core_pos() no longer needs to be called
within the driver, helping with performance a bit.
Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6af
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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| #
22d12c41 |
| 03-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "drivers: add a driver for snoop control unit" into integration
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| #
c20c0525 |
| 13-Dec-2019 |
Vishnu Banavath <vishnu.banavath@arm.com> |
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data c
drivers: add a driver for snoop control unit
The SCU connects one to four Cortex-A5/Cortex-A9 processors
to the memory system through the AXI interfaces.
The SCU functions are to:
- maintain data cache coherency between the Cortex-A5/Cortex-A9
processors
- initiate L2 AXI memory accesses
- arbitrate between Cortex-A5/Cortex-A9 processors requesting
L2 accesses
- manage ACP accesses.
Snoop Control Unit will enable to snoop on other CPUs caches.
This is very important when it comes to synchronizing data between
CPUs. As an example, there is a high chance that data might be
cache'd and other CPUs can't see the change. In such cases,
if snoop control unit is enabled, data is synchoronized immediately
between CPUs and the changes are visible to other CPUs.
This driver provides functionality to enable SCU as well as enabling
user to know the following
- number of CPUs present
- is a particular CPU operating in SMP mode or AMP mode
- data cache size of a particular CPU
- does SCU has ACP port
- is L2CPRESENT
Change-Id: I0d977970154fa60df57caf449200d471f02312a0
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
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| #
7a8ef89f |
| 17-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "plat/arm: Introduce A5 DesignStart platform." into integration
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| #
00c7d5ac |
| 18-Jun-2019 |
Usama Arif <usama.arif@arm.com> |
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with
plat/arm: Introduce A5 DesignStart platform.
This patch adds support for Cortex-A5 FVP for the
DesignStart program. DesignStart aims at providing
low cost and fast access to Arm IP.
Currently with this patch only the primary CPU is booted
and the rest of them wait for an interrupt.
Signed-off-by: Usama Arif <usama.arif@arm.com>
Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab
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