refactor: convert arm platforms to use the generic GIC driverThis reduces the code the platforms have to carry and makes their buildrules a bit simpler.The main benefit is that plat_my_core_pos(
refactor: convert arm platforms to use the generic GIC driverThis reduces the code the platforms have to carry and makes their buildrules a bit simpler.The main benefit is that plat_my_core_pos() no longer needs to be calledwithin the driver, helping with performance a bit.Change-Id: I0b0d1d36d20d67c41c8c9dc14ade11bda6d4a6afSigned-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
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refactor(arm): simplify early platform setup functionsRefactor `arm_sp_min_early_platform_setup` to accept generic`u_register_r` values to support receiving firmware handoff bootarguments in comm
refactor(arm): simplify early platform setup functionsRefactor `arm_sp_min_early_platform_setup` to accept generic`u_register_r` values to support receiving firmware handoff bootarguments in common code. This has the added benefit of simplifying theinterface into common early platform setup.Change-Id: Idfc3d41f94f2bf3a3a0c7ca39f6b9b0013836e3aSigned-off-by: Harrison Mutai <harrison.mutai@arm.com>
drivers: add a driver for snoop control unitThe SCU connects one to four Cortex-A5/Cortex-A9 processorsto the memory system through the AXI interfaces.The SCU functions are to:- maintain data c
drivers: add a driver for snoop control unitThe SCU connects one to four Cortex-A5/Cortex-A9 processorsto the memory system through the AXI interfaces.The SCU functions are to:- maintain data cache coherency between the Cortex-A5/Cortex-A9 processors- initiate L2 AXI memory accesses- arbitrate between Cortex-A5/Cortex-A9 processors requesting L2 accesses- manage ACP accesses.Snoop Control Unit will enable to snoop on other CPUs caches.This is very important when it comes to synchronizing data betweenCPUs. As an example, there is a high chance that data might becache'd and other CPUs can't see the change. In such cases,if snoop control unit is enabled, data is synchoronized immediatelybetween CPUs and the changes are visible to other CPUs.This driver provides functionality to enable SCU as well as enablinguser to know the following- number of CPUs present- is a particular CPU operating in SMP mode or AMP mode- data cache size of a particular CPU- does SCU has ACP port- is L2CPRESENTChange-Id: I0d977970154fa60df57caf449200d471f02312a0Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
plat/arm: Introduce A5 DesignStart platform.This patch adds support for Cortex-A5 FVP for theDesignStart program. DesignStart aims at providinglow cost and fast access to Arm IP.Currently with
plat/arm: Introduce A5 DesignStart platform.This patch adds support for Cortex-A5 FVP for theDesignStart program. DesignStart aims at providinglow cost and fast access to Arm IP.Currently with this patch only the primary CPU is bootedand the rest of them wait for an interrupt.Signed-off-by: Usama Arif <usama.arif@arm.com>Change-Id: I3a2281ce6de2402dda4610a89939ed53aa045fab