refactor(versal2): add tfa_no_pm flag for scmi

Added the TFA_NO_PM flag in the SCMI file and guarded SCMI
functionality with if conditions. When TFA_NO_PM is set to 0
(default), Platform Management

refactor(versal2): add tfa_no_pm flag for scmi

Added the TFA_NO_PM flag in the SCMI file and guarded SCMI
functionality with if conditions. When TFA_NO_PM is set to 0
(default), Platform Management is enabled. When set to 1, Platform
Management is disabled. This allows the generic SCMI driver to be
used in non-PM scenarios while maintaining compatibility with
conforming power management interfaces.

Change-Id: I4f6483e2c8a322ecb41e523bc03a351af4a2cb6b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces

refactor(arm): unify SPSR retrieval logic

Consolidate platform-specific SPSR setup logic into a single
arm_get_spsr() function that accepts an image_id to select between BL32
and BL33. This reduces duplication and simplifies control over SPSR
generation for later stages, particularly BL33.

The SPD remains responsible for setting the SPSR for BL32.

Change-Id: Ibbba708d607e7676989f5c7ceffe33d7bb2195f1
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(versal2): validate non-secure entry addr

Added validate_ns_entrypoint to get reserved-memory entries from
the Flattened Device Tree (FDT). Identifies secure and non-secure
memory regions and ch

feat(versal2): validate non-secure entry addr

Added validate_ns_entrypoint to get reserved-memory entries from
the Flattened Device Tree (FDT). Identifies secure and non-secure
memory regions and checks if entry point lies within a valid
non-secure region.

Change-Id: Iff998fe855f5de8fbd96f0d7d4b0d7c33c904d34
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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feat(versal2): parse reserve memory subnodes

In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point

feat(versal2): parse reserve memory subnodes

In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point address during a hot plug event

Change-Id: I8cdb098509bd3b06f0df5ea647220bdbb8a4bf35
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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Merge "fix(xilinx): add API to get powerdown request status" into integration

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and pl

build(handoff)!: switch to LibTL submodule

Removes in-tree Transfer List implementation and updates all references
to use the external LibTL submodule. Updates include paths, Makefile
macros, and platform integration logic to link with LibTL as a static
library.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: LibTL is now included in TF-A as a submodule.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: I1fa31f7b730066c27985d968698e553b00b07c38
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes Ia34bc0f4,I0be3773b,I701e357a,Icdbe1992 into integration

* changes:
refactor(versal2): guard handoff logic w/ build flag
refactor(qemu): guard handoff logic w/ build flag
refacto

Merge changes Ia34bc0f4,I0be3773b,I701e357a,Icdbe1992 into integration

* changes:
refactor(versal2): guard handoff logic w/ build flag
refactor(qemu): guard handoff logic w/ build flag
refactor(optee): guard handoff logic w/ build flag
feat(handoff): support libtl submodule builds

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fix(xilinx): add API to get powerdown request status

The pwrdwn_req_received variable is used across multiple platforms
through extern keyword. Instead of using the extern, add getter
API to access

fix(xilinx): add API to get powerdown request status

The pwrdwn_req_received variable is used across multiple platforms
through extern keyword. Instead of using the extern, add getter
API to access this variable across the platforms, and restrict the
scope of variable to the particular file by defining it as static
variable. This prevents unintended access of variable from other
files and increase safety.

Change-Id: I758466ea7f6be2a90ec249dc3e4fa56cdbe11e57
Signed-off-by: Devanshi Chauhan <devanshi.chauhanalpeshbhai@amd.com>

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refactor(versal2): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSF

refactor(versal2): guard handoff logic w/ build flag

Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSFER_LIST` guards, ensuring the platform can build and run without
the submodule.

This is useful for builds not integrating the firmware handoff
mechanism.

Change-Id: Ia34bc0f4d352a3014c71eda6589c0f3e0a107ca0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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Merge changes from topic "validate node ID in PM events" into integration

* changes:
fix(versal2): validate Node ID in PM callback events
fix(xilinx): validate Node ID in PM callback events
fi

Merge changes from topic "validate node ID in PM events" into integration

* changes:
fix(versal2): validate Node ID in PM callback events
fix(xilinx): validate Node ID in PM callback events
fix(xilinx): add macro to extract node class from node ID

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fix(versal2): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
disting

fix(versal2): validate Node ID in PM callback events

The PM_NOTIFY_CB is used to notify both events and errors from the PLM
firmware. The values of events and errors can overlap, they can be
distinguished using the Node ID, which is included in the callback payload.

Currently, when an EVENT_CPU_PWRDWN notification is received, TF-A powers
down cores without validating the Node ID. This leads to incorrect
behavior, as TFA powers down cores even when an error occurs that shares
the same event value.

Add a Node ID check to differentiate between events and errors to fix
this issue.

Change-Id: I65d69731b692928597e47678c684aea2b90b5e6d
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but t

fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but the actual register offsets are
non-linear: 0, 1, 4, 5, 8, 9, 12, 13. As a result, the system
mistakenly disables wakeup and power down interrupts for other
cores. So convert the linear cpuid to a non-linear mapping and
update the APU_PCIL offset macros accordingly.

Change-Id: Ifd823f51d70d9d03fa87cc35ccc733a462eae36a
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer fre

fix(versal2): initialize counter-timer frequency register

During initialization CNTFRQ_EL0 value is not getting updated and
its remaining 0. Because of that Linux is not able to get system
timer frequency and cpu idle with cpu power down state is not
working. So update CNTFRQ_EL0 value during initialization.

Change-Id: I238f67521bbc338c433ce18f60df51efc4c5f387
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq,

fix(versal2): use common function to get system counter frequency

Currently, the IOU_SCNTR system counter frequency value is not read from
plat_get_syscnt_freq2(), and it returns the local cpu_freq, which is
incorrect. Use the common plat_get_syscnt_freq2() to read the IOU_SCNTR
frequency register and return the correct value.

Change-Id: I277dc6a2e4acd1acd3f048aaf242a3580d06e1c8
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consist

fix(versal2): align IOU_SCNTR base address macro name with other platforms

Renamed the IOU_SCNTR base address macro to match the naming
convention used in Versal and Versal NET. This ensures
consistency across platforms and enables the use of a common
function for getting and setting the system counter-timer
frequency.

Change-Id: I257a1086d77350858d63859b0fbe6e2b47deb9e5
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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fix(xilinx): resolve misra rule 4.5 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.5:
- Identifiers in the same name space with overlapping visibility should
be ty

fix(xilinx): resolve misra rule 4.5 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.4.5:
- Identifiers in the same name space with overlapping visibility should
be typographically unambiguous.
- Fix:
- Renamed PM_RET_ERROR_NOFEATURE to PM_RET_ERROR_IOCTL_NOT_SUPPORTED
and removed unnecessary macro definitions.

Change-Id: I6f03e619979685df7418fbccad7b0934d136776e
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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Merge changes from topic "xlnx_fix_chore" into integration

* changes:
chore(versal2): realign address printing
fix(amd): update transfer list args for OP-TEE

Merge changes from topic "xlnx_versal2_ipi" into integration

* changes:
feat(versal2): add bufferless IPI Support
chore(versal2): use BIT_32() macro

Merge "fix(versal2): enable system reset" into integration

fix(xilinx): resolve misra rule 10.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic conversions
ar

fix(xilinx): resolve misra rule 10.4 violations

Fixed below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic conversions
are performed shall have the same essential type category.
- Fix:
- Made data type same for both the operands.

Change-Id: I0cea19477f3c10265d95ea1d5d2ea151dbf174bb
Signed-off-by: Devanshi Chauhan Alpeshbhai <devanshi.chauhanalpeshbhai@amd.com>

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fix(versal2): enable system reset

The commit 414cf08b76bc ("feat(versal2): add support for platform
management") changed how system reset works by requiring
pwrdwn_req_received to be set for TF-A to

fix(versal2): enable system reset

The commit 414cf08b76bc ("feat(versal2): add support for platform
management") changed how system reset works by requiring
pwrdwn_req_received to be set for TF-A to make a call to PLM firmware.

This accidentally blocked reset initiated by Linux or U-Boot,
as this flag is only set during PLM firmware initiated reset.

Fix this issue by enabling firmware call when pwrdwn_req_received
is not set, ensuring Linux and U-Boot can initiate reset properly.

Fixes: 414cf08b76bc ("feat(versal2): add support for platform management")
Change-Id: I6ffc9b2efa56a7bd843b296e2c892c064ffd054a
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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feat(versal2): add bufferless IPI Support

Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.

Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.

Change-Id: I1dc11c8473c390a517fdd3a9

feat(versal2): add bufferless IPI Support

Versal Gen 2 SOC has same IPI mapping as Versal NET SOC.

Ports the bufferless Versal NET IPI mapping to
Versal Gen 2.

Change-Id: I1dc11c8473c390a517fdd3a9e4fc35dc5563792b
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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chore(versal2): use BIT_32() macro

Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.

Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levin

chore(versal2): use BIT_32() macro

Use BIT_32() macro for readability for Versal Gen 2 IPI Bit positions.

Change-Id: I69718b22de890519e906be185f593b4fd9df1be5
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>

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Merge "feat(versal2): is OCM configured as coherent" into integration

fix(versal2): align QEMU APU GT frequency with silicon

The APU generic timer frequency in QEMU is now aligned on silicon to the
value of 100MHz.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Chang

fix(versal2): align QEMU APU GT frequency with silicon

The APU generic timer frequency in QEMU is now aligned on silicon to the
value of 100MHz.

Signed-off-by: Luc Michel <luc.michel@amd.com>
Change-Id: I4ef0a040c14fdb2fbb3f2d9d4e6ca6ee8ac8e229

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