Merge changes from topic "xlnx_remove_abort_suspend" into integration

* changes:
fix(versal-net): remove client-side code of PM_ABORT_SUSPEND
fix(versal): remove client-side implementation of PM

Merge changes from topic "xlnx_remove_abort_suspend" into integration

* changes:
fix(versal-net): remove client-side code of PM_ABORT_SUSPEND
fix(versal): remove client-side implementation of PM_ABORT_SUSPEND
fix(xilinx): remove PM_ABORT_SUSPEND API implementation
fix(zynqmp): remove PM_ABORT_SUSPEND API implementation
fix(versal2): remove PM_ABORT_SUSPEND API implementation

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fix(versal2): remove PM_ABORT_SUSPEND API implementation

The API is not getting called by Linux. Removing it to reduce dead
code and improve maintainability.

Change-Id: I88025fa0213e40c510a2f1edb65

fix(versal2): remove PM_ABORT_SUSPEND API implementation

The API is not getting called by Linux. Removing it to reduce dead
code and improve maintainability.

Change-Id: I88025fa0213e40c510a2f1edb6566fc849a8dbb6
Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>

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Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG

Merge changes from topic "xlnx_enhancement_on_secure_and_non_secure_flag" into integration

* changes:
feat(xilinx): use common SECURE/NON_SECURE macro
fix(xilinx): incorrect usage of SECURE_FLAG for psci

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge changes I5fcf6578,Ic7792603 into integration

* changes:
fix(xilinx): fix missing security flag in suspend path
feat(zynqmp): mark IPI calls secure/non-secure

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This ma

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This may cause incorrect behavior for non-secure
suspend requests.

Fix this by passing the caller's security state (flag) through
pm_client_suspend() and pm_client_set_wakeup_sources() to ensure
that wakeup sources are set with the correct context.

Fixes: <4697164a3fa8> ("plat: xilinx: versal: Mark IPI calls secure/non-secure")

Change-Id: I5fcf65788a54010b4759b0d08e4f54c6e5037e47
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge "feat(versal2): add support of MMI_GEM as wakeup source" into integration

feat(versal2): add support of MMI_GEM as wakeup source

Add MMI_GEM device node ID and add support of MMI_GEM as wakeup
source.

Change-Id: I449e23df63e887978be1ff6d151542a27c44466f
Signed-off-by: Na

feat(versal2): add support of MMI_GEM as wakeup source

Add MMI_GEM device node ID and add support of MMI_GEM as wakeup
source.

Change-Id: I449e23df63e887978be1ff6d151542a27c44466f
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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Merge changes from topic "xlnx_versal2_cpuidle_fix" into integration

* changes:
fix(versal2): fix offsets for apu pcil
fix(versal2): initialize counter-timer frequency register
fix(versal2): u

Merge changes from topic "xlnx_versal2_cpuidle_fix" into integration

* changes:
fix(versal2): fix offsets for apu pcil
fix(versal2): initialize counter-timer frequency register
fix(versal2): use common function to get system counter frequency
fix(versal2): align IOU_SCNTR base address macro name with other platforms

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fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but t

fix(versal2): fix offsets for apu pcil

The current APU_PCIL offsets for disabling power down and wakeup
interrupts are incorrect. The cpuid passed to the register offset
macro is linear (0-8), but the actual register offsets are
non-linear: 0, 1, 4, 5, 8, 9, 12, 13. As a result, the system
mistakenly disables wakeup and power down interrupts for other
cores. So convert the linear cpuid to a non-linear mapping and
update the APU_PCIL offset macros accordingly.

Change-Id: Ifd823f51d70d9d03fa87cc35ccc733a462eae36a
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>

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Merge changes from topic "versal2-pm-support" into integration

* changes:
feat(versal2): extended SMCCC payload for EEMI
feat(versal2): add support for platform management
feat(versal2): add d

Merge changes from topic "versal2-pm-support" into integration

* changes:
feat(versal2): extended SMCCC payload for EEMI
feat(versal2): add support for platform management
feat(versal2): add dependency macro for PM

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feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM func

feat(versal2): add support for platform management

Add support for PM functionality through EEMI interface for
Versal Gen 2. Add support of PM APIs in PSCI ops. Add
TFA_NO_PM flag to disable PM functionality. Enable wakeup for
new peripherals

Change-Id: I1bf67dc46af91ee113c627d32ae6ecc1dad386c2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>

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