fix(versal2): fix misra rule 5.7 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.5.7:
- A tag name shall be a unique identifier.
- Fix:
- Rename local variables to avoid

fix(versal2): fix misra rule 5.7 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.5.7:
- A tag name shall be a unique identifier.
- Fix:
- Rename local variables to avoid conflict with type names.

Change-Id: Iac8df3166dcc69ceccaaddae2134f9c8a043b3b6
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(versal2): fix misra rule 10.4 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic
conversions are per

fix(versal2): fix misra rule 10.4 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
- Fix:
- Make operands of the same essential type category.

Change-Id: Idf3489dee8f45a5a27bda4e4392b84510352623e
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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fix(versal2): fix misra rule 10.3 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower

fix(versal2): fix misra rule 10.3 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category.
- Fix:
- Add explicit type casts to prevent implicit narrowing
conversions.

Change-Id: I756137cf9a403f1f6395c1d7c2d9bb70a3f6ff80
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

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feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the p

feat(versal2): support alternate core as primary (non-cpu0)

Primary core was hardcoded to CPU0, causing a panic when another
core booted first.
Update logic to allow any booting core to become the primary and
gate secondary core startup inline to existing implementation for
secondary cores.

Change-Id: I6a5d76f23d4d4c4139d95bbaf55edf1244f2dbfe
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>

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fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): renam

fix(versal2): align comment about invalid console selection

Error message should be aligned actual symbol used for console section
which has been changed by commit 2333ab4cd214 ("fix(versal2): rename
console build arg to generic").

Change-Id: I230892875a6343ca8ffc55e0fac251f6586cf3f4
Signed-off-by: Michal Simek <michal.simek@amd.com>

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fix(versal2): remove PM_ABORT_SUSPEND API implementation

The API is not getting called by Linux. Removing it to reduce dead
code and improve maintainability.

Change-Id: I88025fa0213e40c510a2f1edb65

fix(versal2): remove PM_ABORT_SUSPEND API implementation

The API is not getting called by Linux. Removing it to reduce dead
code and improve maintainability.

Change-Id: I88025fa0213e40c510a2f1edb6566fc849a8dbb6
Signed-off-by: Madhav Bhatt <madhav.bhatt@amd.com>

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fix(versal2): enable graceful system shutdown

Power down the APU cores before sending SYSTEM_SHUTDOWN call to
PLM firmware. This ensures graceful system shutdown.

Change-Id: I89a132e72c9a2530620ffb

fix(versal2): enable graceful system shutdown

Power down the APU cores before sending SYSTEM_SHUTDOWN call to
PLM firmware. This ensures graceful system shutdown.

Change-Id: I89a132e72c9a2530620ffb58aaec752796d01d3e
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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Merge changes from topic "xlnx_enhance_tfa_feature_check" into integration

* changes:
chore(xilinx): add deprecation warning to pm_feature_check
refactor(xilinx): rename eemi_feature_check to tf

Merge changes from topic "xlnx_enhance_tfa_feature_check" into integration

* changes:
chore(xilinx): add deprecation warning to pm_feature_check
refactor(xilinx): rename eemi_feature_check to tfa_api_feature_check

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fix(versal2): handle debugfs specific APIs before EEMI handler

In Versal Gen 2 SoC, all PM APIs use the extended SMC format including
the debugfs-specific APIs. So, call eemi_psci_debugfs_handler be

fix(versal2): handle debugfs specific APIs before EEMI handler

In Versal Gen 2 SoC, all PM APIs use the extended SMC format including
the debugfs-specific APIs. So, call eemi_psci_debugfs_handler before
eemi_api_handler. This ensures that debugfs-specific PM APIs are handled
correctly by TF-A and are not forwarded to the PLM firmware.

Change-Id: Ibab08c851c853a8f4272783b210040ddf7291d76
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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fix(versal2): use PM_STATE_CPU_OFF for core power down in SELF_SUSPEND

Currently TF-A provides PM_STATE_CPU_IDLE state during SELF_SUSPEND
to power down the core. PM_STATE_CPU_IDLE is intended for C

fix(versal2): use PM_STATE_CPU_OFF for core power down in SELF_SUSPEND

Currently TF-A provides PM_STATE_CPU_IDLE state during SELF_SUSPEND
to power down the core. PM_STATE_CPU_IDLE is intended for CPU-idle
suspend paths (when Linux CPU idle is enabled) and is not the correct
state for a full core power-off.

Fix this by providing PM_STATE_CPU_OFF state to power down the core.

Change-Id: I25585b32fe90372b0404a1ad89544f1aaa2f34a2
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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refactor(xilinx): rename eemi_feature_check to tfa_api_feature_check

Rename eemi_feature_check() to tfa_api_feature_check() for better
clarity. The new name clearly indicates its purpose of handling

refactor(xilinx): rename eemi_feature_check to tfa_api_feature_check

Rename eemi_feature_check() to tfa_api_feature_check() for better
clarity. The new name clearly indicates its purpose of handling TF-A
specific feature checks and improves code maintainability.

Change-Id: Ia74b12933427ccadbc8ede5ddc2a7a4822766264
Signed-off-by: Devanshi Chauhan <devanshi.chauhan@amd.com>

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feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE acr

feat(xilinx): use common SECURE/NON_SECURE macro

Remove platform-specific macro definitions such as SECURE_FLAG and
NON_SECURE_FLAG, and replace them with the common macros SECURE and
NON_SECURE across all AMD-Xilinx platforms.

Change-Id: I95465e29ac8a9370da135c2113203c3206ecfec0
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was

fix(xilinx): incorrect usage of SECURE_FLAG for psci

As per the PSCI specification, the PSCI SMC call always expects from
the NON_SECURE world. However, in the platform specific file SECURE
flag was passed to the firmware which is incorrect. Pass NON_SECURE
flag from the platform specific file to the firmware in order to
align with the PSCI specification.

Change-Id: Iabe2cb45467cf63fe36626d323513ff05548eb3b
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API

Deprecate the use of the PM_REQ_SUSPEND EEMI API from the Versal,
Versal-Net and Versal Gen 2 platforms. This is because the API is
intended for suspe

feat(xilinx): deprecate PM_REQ_SUSPEND EEMI API

Deprecate the use of the PM_REQ_SUSPEND EEMI API from the Versal,
Versal-Net and Versal Gen 2 platforms. This is because the API is
intended for suspending cross-subsystems, and the same functionality
can now be achieved using the ForcePowerdown API. Therefore,
continuing to use PM_REQ_SUSPEND API may no longer be necessary.
Hence deprecating the same.

Change-Id: I967d7803da4cf433fabfe8d87c32305954f69884
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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Merge "chore(versal2): rename versal2 to Versal Gen 2" into integration

Merge changes I5fcf6578,Ic7792603 into integration

* changes:
fix(xilinx): fix missing security flag in suspend path
feat(zynqmp): mark IPI calls secure/non-secure

chore(versal2): rename versal2 to Versal Gen 2

The term Versal2 should be updated to Versal Gen 2.

Change-Id: Iac94ef32604f88ec030bf95ec35484b72a0f7ffa
Signed-off-by: Prasad Kummari <prasad.kummari

chore(versal2): rename versal2 to Versal Gen 2

The term Versal2 should be updated to Versal Gen 2.

Change-Id: Iac94ef32604f88ec030bf95ec35484b72a0f7ffa
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization.

feat(versal2): add SPMD support for SPMC at S-EL1

Added support for SPMD when SPMC is running at S-EL1 on Versal Gen 2
platform. Added DTB with manifest addresses to BL32 for proper
initialization. Added `plat_spmd_handle_group0_interrupt` to handle
Group0 interrupts in SPMD. Added a new manifest source file compliant
with FFA 1.0 specification in which load_address and entrypoint
points to BL32 base address.

Change-Id: I518e2e799d3b86fcd67f9fee0af42503ca705488
Signed-off-by: Pranav Tilak <pranav.vinaytilak@amd.com>

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fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This ma

fix(xilinx): fix missing security flag in suspend path

Suspend flow was always programming wakeup sources with a fixed
secure flag, regardless of whether the caller was secure or
non-secure. This may cause incorrect behavior for non-secure
suspend requests.

Fix this by passing the caller's security state (flag) through
pm_client_suspend() and pm_client_set_wakeup_sources() to ensure
that wakeup sources are set with the correct context.

Fixes: <4697164a3fa8> ("plat: xilinx: versal: Mark IPI calls secure/non-secure")

Change-Id: I5fcf65788a54010b4759b0d08e4f54c6e5037e47
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

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fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from

fix(versal2): move plat_core_pos_by_mpidr to asm

In the current implementation, plat_core_pos_by_mpidr() is defined in
C.When BL31 is compiled with Armclang, a call to plat_core_pos_by_mpidr()
from plat_my_core_pos() results in the return address stored in register
x30 becoming invalid and register x9 (used later) ends up with the value
0x0. Consequently, the CPU branches to address 0x0, triggering a
synchronous exception. TF-A then invokes the BHB flush code before
resuming execution. However, since the stack is not properly initialized
at this stage, the system eventually enters plat_panic_handler().
In the updated implementation, the platform_get_core_pos() function
is redefined in assembly to provide tighter control during early boot
stages. The MPIDR_EL1 register contains three affinity levels: Aff0
(bits [0:7]), Aff1 (bits [8:15]), and Aff2 (bits [16:23]). In this
assembly function, the core ID is extracted from Aff1
(MPIDR_AFF1_SHIFT), and the cluster ID from Aff2 (MPIDR_AFF2_SHIFT).
cluster/core ID calculation. The macro PLATFORM_MPIDR_AFFINITY_MASK
introduced to mask MPIDR_EL1 register.

Change-Id: Id532bbcd68f18e87ceba01c8f961d8c15962a1a3
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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fix(versal2): runtime console in debug mode

Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to
pl011, regardless of the user-specified CONSOLE value. This causes a
build requested wi

fix(versal2): runtime console in debug mode

Whenever DEBUG is set to 1, the Makefile forces CONSOLE_RUNTIME to
pl011, regardless of the user-specified CONSOLE value. This causes a
build requested with CONSOLE=pl011_1 to register both pl011_1 and
pl011 as boot and runtime consoles. If the hardware is connected only
to UART1, this causes TF-A to hang when UART0 is selected as the
runtime console, since it waits indefinitely on the transmit FIFO.
The fix ensures that, in a DEBUG build, CONSOLE_RUNTIME defaults to
the same value as CONSOLE.

Change-Id: I2e29d5b77c43aa65f58224d226683f4a8d94271a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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Merge "fix(versal2): remove extraneous parentheses" into integration

Merge "feat(versal2): add support of MMI_GEM as wakeup source" into integration

fix(versal2): remove extraneous parentheses

While compiling TF-A with Armclang, the following error was observed.
To fix it, the extraneous parentheses around the comparison were
removed to silence

fix(versal2): remove extraneous parentheses

While compiling TF-A with Armclang, the following error was observed.
To fix it, the extraneous parentheses around the comparison were
removed to silence the warning.

plat/amd/versal2/scmi.c:322:13: error: equality comparison with
extraneous parentheses [-Werror,-Wparentheses-equality]
if ((clock == NULL)) {

Change-Id: I51f955dd15d5020598c9e4ff2f7f92b55a909f9b
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

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feat(versal2): add support of MMI_GEM as wakeup source

Add MMI_GEM device node ID and add support of MMI_GEM as wakeup
source.

Change-Id: I449e23df63e887978be1ff6d151542a27c44466f
Signed-off-by: Na

feat(versal2): add support of MMI_GEM as wakeup source

Add MMI_GEM device node ID and add support of MMI_GEM as wakeup
source.

Change-Id: I449e23df63e887978be1ff6d151542a27c44466f
Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>

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