| #
9cc15390 |
| 03-Jul-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_fix_plat_ns_entry" into integration
* changes:
feat(versal2): validate non-secure entry addr
feat(versal2): parse reserve memory subnodes
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| #
59eaed03 |
| 25-Jun-2025 |
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> |
feat(versal2): parse reserve memory subnodes
In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point
feat(versal2): parse reserve memory subnodes
In Versal Gen 2, TF-A parses the device tree to identify secure and
non-secure memory regions, which are then used to validate the
non-secure entry point address during a hot plug event
Change-Id: I8cdb098509bd3b06f0df5ea647220bdbb8a4bf35
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
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| #
50d1ce3d |
| 19-Jun-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes Ia34bc0f4,I0be3773b,I701e357a,Icdbe1992 into integration
* changes:
refactor(versal2): guard handoff logic w/ build flag
refactor(qemu): guard handoff logic w/ build flag
refacto
Merge changes Ia34bc0f4,I0be3773b,I701e357a,Icdbe1992 into integration
* changes:
refactor(versal2): guard handoff logic w/ build flag
refactor(qemu): guard handoff logic w/ build flag
refactor(optee): guard handoff logic w/ build flag
feat(handoff): support libtl submodule builds
show more ...
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| #
e7dd086f |
| 27-May-2025 |
Harrison Mutai <harrison.mutai@arm.com> |
refactor(versal2): guard handoff logic w/ build flag
Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSF
refactor(versal2): guard handoff logic w/ build flag
Prepare for environments where the Firmware Handoff (LibTL) submodule
may not be available. Wrap all Transfer List dependent logic in `#if
TRANSFER_LIST` guards, ensuring the platform can build and run without
the submodule.
This is useful for builds not integrating the firmware handoff
mechanism.
Change-Id: Ia34bc0f4d352a3014c71eda6589c0f3e0a107ca0
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
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| #
7a6230c1 |
| 17-Feb-2025 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration
* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refacto
Merge changes from topic "xlnx_fix_plat_ret_dt_tl" into integration
* changes:
fix(versal2): pass tl address to bl32
fix(xilinx): runtime console to handle dt failure
refactor(xilinx): refactor console to support transfer list
chore(xilinx): propagate error code
feat(versal2): retrieve DT address from transfer list
chore(versal2): move xfer-list file paths
fix(versal2): update transfer list as optional
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| #
ea453871 |
| 04-Dec-2024 |
Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com> |
feat(versal2): retrieve DT address from transfer list
On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.
Change-Id: I44
feat(versal2): retrieve DT address from transfer list
On versal2 platform, unlike current static DT address passing
mechanism, DT address is retrieved from transfer list dynamically.
Change-Id: I44b9a0753809652f26bc1b7e061f5364229ba352
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
show more ...
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